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authorIngo Molnar <mingo@elte.hu>2011-04-21 11:39:21 +0200
committerIngo Molnar <mingo@elte.hu>2011-04-21 11:39:28 +0200
commit42ac9e87fdd89b77fa2ca0a5226023c1c2d83226 (patch)
treedfdb1b720347a40f24a89a3e9c2727ae26ad5f01 /arch/blackfin/mach-common
parent057f3fadb347e9c51b07e1b277bbdda79f976768 (diff)
parentf0e615c3cb72b42191b558c130409335812621d8 (diff)
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Merge commit 'v2.6.39-rc4' into sched/core
Merge reason: Pick up upstream fixes. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/blackfin/mach-common')
-rw-r--r--arch/blackfin/mach-common/smp.c19
1 files changed, 16 insertions, 3 deletions
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 326bb86..1fbd94c 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -109,10 +109,23 @@ static void ipi_flush_icache(void *info)
struct blackfin_flush_data *fdata = info;
/* Invalidate the memory holding the bounds of the flushed region. */
- invalidate_dcache_range((unsigned long)fdata,
- (unsigned long)fdata + sizeof(*fdata));
+ blackfin_dcache_invalidate_range((unsigned long)fdata,
+ (unsigned long)fdata + sizeof(*fdata));
+
+ /* Make sure all write buffers in the data side of the core
+ * are flushed before trying to invalidate the icache. This
+ * needs to be after the data flush and before the icache
+ * flush so that the SSYNC does the right thing in preventing
+ * the instruction prefetcher from hitting things in cached
+ * memory at the wrong time -- it runs much further ahead than
+ * the pipeline.
+ */
+ SSYNC();
- flush_icache_range(fdata->start, fdata->end);
+ /* ipi_flaush_icache is invoked by generic flush_icache_range,
+ * so call blackfin arch icache flush directly here.
+ */
+ blackfin_icache_flush_range(fdata->start, fdata->end);
}
static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)