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| author | Chris Metcalf <cmetcalf@tilera.com> | 2010-11-02 12:05:10 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2010-11-24 13:13:49 -0500 |
| commit | f02cbbe657939489347cbda598401a56913ffcbd (patch) | |
| tree | 0d21e68d899958e6549f908b0c715c6f37200027 /arch/frv | |
| parent | e5a06939736277c54a68ae275433db55b99d187c (diff) | |
| download | kernel_goldelico_gta04-f02cbbe657939489347cbda598401a56913ffcbd.zip kernel_goldelico_gta04-f02cbbe657939489347cbda598401a56913ffcbd.tar.gz kernel_goldelico_gta04-f02cbbe657939489347cbda598401a56913ffcbd.tar.bz2 | |
pci root complex: support for tile architecture
This change enables PCI root complex support for TILEPro. Unlike
TILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI
support consists of hypervisor upcalls for PIO, DMA, etc. However,
the performance is fine for the devices we have tested with so far
(1Gb Ethernet, SATA, etc.).
The <asm/io.h> header was tweaked to be a little bit more aggressive
about disabling attempts to map/unmap IO port space. The hacky
<asm/pci-bridge.h> header was rolled into the <asm/pci.h> header
and the result was simplified. Both of the latter two headers were
preliminary versions not meant for release before now - oh well.
There is one quirk for our TILEmpower platform, which accidentally
negotiates up to 5GT and needs to be kicked down to 2.5GT.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/frv')
0 files changed, 0 insertions, 0 deletions