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| author | Bob Moore <robert.moore@intel.com> | 2005-10-21 00:00:00 -0400 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2005-12-10 00:22:54 -0500 |
| commit | 0897831bb54eb36fd9e2a22da7f0f64be1b20d09 (patch) | |
| tree | 8d77687ce8ebcfb62d6012d2d3c44f6a904b3c15 /arch/ia64/pci | |
| parent | 50eca3eb89d73d9f0aa070b126c7ee6a616016ab (diff) | |
| download | kernel_goldelico_gta04-0897831bb54eb36fd9e2a22da7f0f64be1b20d09.zip kernel_goldelico_gta04-0897831bb54eb36fd9e2a22da7f0f64be1b20d09.tar.gz kernel_goldelico_gta04-0897831bb54eb36fd9e2a22da7f0f64be1b20d09.tar.bz2 | |
[ACPI] ACPICA 20051021
Implemented support for the EM64T and other x86_64
processors. This essentially entails recognizing
that these processors support non-aligned memory
transfers. Previously, all 64-bit processors were assumed
to lack hardware support for non-aligned transfers.
Completed conversion of the Resource Manager to nearly
full table-driven operation. Specifically, the resource
conversion code (convert AML to internal format and the
reverse) and the debug code to dump internal resource
descriptors are fully table-driven, reducing code and data
size and improving maintainability.
The OSL interfaces for Acquire and Release Lock now use a
64-bit flag word on 64-bit processors instead of a fixed
32-bit word. (Alexey Starikovskiy)
Implemented support within the resource conversion code
for the Type-Specific byte within the various ACPI 3.0
*WordSpace macros.
Fixed some issues within the resource conversion code for
the type-specific flags for both Memory and I/O address
resource descriptors. For Memory, implemented support
for the MTP and TTP flags. For I/O, split the TRS and TTP
flags into two separate fields.
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/ia64/pci')
| -rw-r--r-- | arch/ia64/pci/pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c index 25f923d..5536027 100644 --- a/arch/ia64/pci/pci.c +++ b/arch/ia64/pci/pci.c @@ -195,7 +195,7 @@ add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr) min = addr->minimum; max = min + addr->address_length - 1; - if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION) + if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) sparse = 1; space_nr = new_space(addr->translation_offset, sparse); |