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| author | Hirokazu Takata <takata@linux-m32r.org> | 2007-05-10 22:22:26 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-11 08:29:33 -0700 |
| commit | 0d4f64681695b0e389f7121eb647b27c602990bc (patch) | |
| tree | 73ba274b97da70c99cf553f22c93c9d85abc0b83 /arch/m32r/mm | |
| parent | 43c09ce7927912c7867617cba0a265beea38a154 (diff) | |
| download | kernel_goldelico_gta04-0d4f64681695b0e389f7121eb647b27c602990bc.zip kernel_goldelico_gta04-0d4f64681695b0e389f7121eb647b27c602990bc.tar.gz kernel_goldelico_gta04-0d4f64681695b0e389f7121eb647b27c602990bc.tar.bz2 | |
m32r: fix tme_handler to check _PAGE_PRESENT bit
Fix the tlb-miss handler (tme_handler) to check _PAGE_PRESENT bit
in order to handle file-mapped or swapped-out pages correctly.
This patch is required to fix unexpected page errors for m32r.
Signed-off-by: Hitoshi Yamamoto <hitoshiy@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/m32r/mm')
| -rw-r--r-- | arch/m32r/mm/mmu.S | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/arch/m32r/mm/mmu.S b/arch/m32r/mm/mmu.S index 8bb74b1..49a6d16 100644 --- a/arch/m32r/mm/mmu.S +++ b/arch/m32r/mm/mmu.S @@ -163,7 +163,8 @@ ENTRY(tme_handler) ; pte_data = (unsigned long)pte_val(*pte); ld r2, @r3 ; r2: pte data - or3 r2, r2, #2 ; _PAGE_PRESENT(=2) + and3 r3, r2, #2 ; _PAGE_PRESENT(=2) check + beqz r3, 3f .fillinsn 5: @@ -264,11 +265,8 @@ ENTRY(tme_handler) ; and3 r1, r1, #0xeff ldi r4, #611 ; _KERNPG_TABLE(=611) - beq r1, r4, 4f ; !pmd_bad(*pmd) ? - .fillinsn -3: - ldi r1, #0 ; r1: pte_data = 0 - bra 5f + bne r1, r4, 3f ; !pmd_bad(*pmd) ? + .fillinsn 4: ; pte = pte_offset(pmd, address); @@ -282,8 +280,10 @@ ENTRY(tme_handler) add r4, r3 ; r4: pte ; pte_data = (unsigned long)pte_val(*pte); ld r1, @r4 ; r1: pte_data - .fillinsn + and3 r3, r1, #2 ; _PAGE_PRESENT(=2) check + beqz r3, 3f + .fillinsn ;; set tlb ; r0: address, r1: pte_data, r2: entry ; r3,r4: (free) @@ -295,8 +295,7 @@ ENTRY(tme_handler) and3 r4, r4, #(MMU_CONTEXT_ASID_MASK) or r3, r4 st r3, @r2 - or3 r4, r1, #2 ; _PAGE_PRESENT(=2) - st r4, @(4,r2) ; set_tlb_data(entry, pte_data); + st r1, @(4,r2) ; set_tlb_data(entry, pte_data); ld r4, @sp+ ld r3, @sp+ @@ -306,6 +305,11 @@ ENTRY(tme_handler) ld sp, @sp+ rte + .fillinsn +3: + ldi r1, #2 ; r1: pte_data = 0 | _PAGE_PRESENT(=2) + bra 5b + #else #error unknown isa configuration #endif |