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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-03-14 10:45:30 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-05-15 17:49:11 +0200 |
| commit | ec9502599cd837c8e4e279585817d1ffb1249126 (patch) | |
| tree | c650946f4508c942cdb03f12a0f9949509199d46 /arch/mips/ath79 | |
| parent | 67644c547fef2739f49c80e5eb1ace82f3e916e2 (diff) | |
| download | kernel_goldelico_gta04-ec9502599cd837c8e4e279585817d1ffb1249126.zip kernel_goldelico_gta04-ec9502599cd837c8e4e279585817d1ffb1249126.tar.gz kernel_goldelico_gta04-ec9502599cd837c8e4e279585817d1ffb1249126.tar.bz2 | |
MIPS: ath79: add PCI registration code for AR934X
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
Cc: linux-mips@linux-mips.org
Cc: mcgrof@infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/3516/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ath79')
| -rw-r--r-- | arch/mips/ath79/Kconfig | 2 | ||||
| -rw-r--r-- | arch/mips/ath79/pci.c | 13 |
2 files changed, 14 insertions, 1 deletions
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 123cc37..ea28e89 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -72,6 +72,8 @@ config SOC_AR933X config SOC_AR934X select USB_ARCH_HAS_EHCI + select HW_HAS_PCI + select PCI_AR724X if PCI def_bool n config PCI_AR724X diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c index bc40070..ca83abd 100644 --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/pci.h> +#include <asm/mach-ath79/ar71xx_regs.h> #include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/irq.h> #include <asm/mach-ath79/pci.h> @@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) if (soc_is_ar71xx()) { ath79_pci_irq_map = ar71xx_pci_irq_map; ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map); - } else if (soc_is_ar724x()) { + } else if (soc_is_ar724x() || + soc_is_ar9342() || + soc_is_ar9344()) { ath79_pci_irq_map = ar724x_pci_irq_map; ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); } else { @@ -115,5 +118,13 @@ int __init ath79_register_pci(void) if (soc_is_ar724x()) return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); + if (soc_is_ar9342() || soc_is_ar9344()) { + u32 bootstrap; + + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); + if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) + return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); + } + return -ENODEV; } |