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| author | David Daney <david.daney@cavium.com> | 2013-05-13 13:56:43 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-05-16 20:34:55 +0200 |
| commit | 8ea6cd7af124ad070b44a7f60e225e45e3f38f79 (patch) | |
| tree | 55363339702ab4e34be9486cc97d725795ea9387 /arch/mips | |
| parent | f722406faae2d073cc1d01063d1123c35425939e (diff) | |
| download | kernel_goldelico_gta04-8ea6cd7af124ad070b44a7f60e225e45e3f38f79.zip kernel_goldelico_gta04-8ea6cd7af124ad070b44a7f60e225e45e3f38f79.tar.gz kernel_goldelico_gta04-8ea6cd7af124ad070b44a7f60e225e45e3f38f79.tar.bz2 | |
Revert "MIPS: microMIPS: Support dynamic ASID sizing."
This reverts commit f6b06d9361a008afb93b97fb3683a6e92d69d0f4.
The next revert depends on this one, so this has to go too.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/5241/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/mm/tlbex.c | 34 |
1 files changed, 2 insertions, 32 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4d46d37..2ad41e9 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -309,32 +309,13 @@ static int check_for_high_segbits __cpuinitdata; static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop, unsigned int i_const) { - unsigned int **p; + unsigned int **p, *ip; for (p = start; p < stop; p++) { -#ifndef CONFIG_CPU_MICROMIPS - unsigned int *ip; - ip = *p; *ip = (*ip & 0xffff0000) | i_const; -#else - unsigned short *ip; - - ip = ((unsigned short *)((unsigned int)*p - 1)); - if ((*ip & 0xf000) == 0x4000) { - *ip &= 0xfff1; - *ip |= (i_const << 1); - } else if ((*ip & 0xf000) == 0x6000) { - *ip &= 0xfff1; - *ip |= ((i_const >> 2) << 1); - } else { - ip++; - *ip = i_const; - } -#endif - local_flush_icache_range((unsigned long)ip, - (unsigned long)ip + sizeof(*ip)); } + local_flush_icache_range((unsigned long)*p, (unsigned long)((*p) + 1)); } #define asid_insn_fixup(section, const) \ @@ -354,14 +335,6 @@ static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, extern asmlinkage void handle_ri_rdhwr_vivt(void); unsigned long *vivt_exc; -#ifdef CONFIG_CPU_MICROMIPS - /* - * Worst case optimised microMIPS addiu instructions support - * only a 3-bit immediate value. - */ - if(inc > 7) - panic("Invalid ASID increment value!"); -#endif asid_insn_fixup(__asid_inc, inc); asid_insn_fixup(__asid_mask, mask); asid_insn_fixup(__asid_version_mask, version_mask); @@ -369,9 +342,6 @@ static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, /* Patch up the 'handle_ri_rdhwr_vivt' handler. */ vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt; -#ifdef CONFIG_CPU_MICROMIPS - vivt_exc = (unsigned long *)((unsigned long) vivt_exc - 1); -#endif vivt_exc++; *vivt_exc = (*vivt_exc & ~mask) | mask; |