diff options
author | Jonas Bonn <jonas@southpole.se> | 2011-06-04 21:56:16 +0300 |
---|---|---|
committer | Jonas Bonn <jonas@southpole.se> | 2011-07-22 18:46:28 +0200 |
commit | 4f246ba30e1a9a31fcfd91d2ab8f5c75f1362bbf (patch) | |
tree | ca9082608d6ba42abd11bb12d068ac816aa2e842 /arch/openrisc/boot | |
parent | 9d02a4283e9ce4e9ca11ff00615bdacdb0515a1a (diff) | |
download | kernel_goldelico_gta04-4f246ba30e1a9a31fcfd91d2ab8f5c75f1362bbf.zip kernel_goldelico_gta04-4f246ba30e1a9a31fcfd91d2ab8f5c75f1362bbf.tar.gz kernel_goldelico_gta04-4f246ba30e1a9a31fcfd91d2ab8f5c75f1362bbf.tar.bz2 |
OpenRISC: Device tree
The OpenRISC architecture uses the device tree infrastructure for the
platform description. This is currently limited to having a device tree
built into the kernel, but work is underway within the OpenRISC project
to define how this device tree blob should be passed into the kernel from
an external resource.
Patch contains a single example DTS file to go with the defconfig for
or1ksim.
Signed-off-by: Jonas Bonn <jonas@southpole.se>
Cc: devicetree-discuss@lists.ozlabs.org
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/openrisc/boot')
-rw-r--r-- | arch/openrisc/boot/dts/or1ksim.dts | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/openrisc/boot/dts/or1ksim.dts b/arch/openrisc/boot/dts/or1ksim.dts new file mode 100644 index 0000000..5d4f902 --- /dev/null +++ b/arch/openrisc/boot/dts/or1ksim.dts @@ -0,0 +1,50 @@ +/dts-v1/; +/ { + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <20000000>; + }; + + enet0: ethoc@92000000 { + compatible = "opencores,ethmac-rtlsvn338"; + reg = <0x92000000 0x100>; + interrupts = <4>; + }; +}; |