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author | Alex Shi <alex.shi@intel.com> | 2012-06-28 09:02:20 +0800 |
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committer | H. Peter Anvin <hpa@zytor.com> | 2012-06-27 19:29:10 -0700 |
commit | 3df3212f9722c7e45c723b9ea231a04ba4dbc47c (patch) | |
tree | cb93a81efb12b91813ed69e86bc5be24ca31de9d /arch/x86/Kconfig.debug | |
parent | c4211f42d3e66875298a5e26a75109878c80f15b (diff) | |
download | kernel_goldelico_gta04-3df3212f9722c7e45c723b9ea231a04ba4dbc47c.zip kernel_goldelico_gta04-3df3212f9722c7e45c723b9ea231a04ba4dbc47c.tar.gz kernel_goldelico_gta04-3df3212f9722c7e45c723b9ea231a04ba4dbc47c.tar.bz2 |
x86/tlb: add tlb_flushall_shift knob into debugfs
kernel will replace cr3 rewrite with invlpg when
tlb_flush_entries <= active_tlb_entries / 2^tlb_flushall_factor
if tlb_flushall_factor is -1, kernel won't do this replacement.
User can modify its value according to specific CPU/applications.
Thanks for Borislav providing the help message of
CONFIG_DEBUG_TLBFLUSH.
Signed-off-by: Alex Shi <alex.shi@intel.com>
Link: http://lkml.kernel.org/r/1340845344-27557-6-git-send-email-alex.shi@intel.com
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/Kconfig.debug')
-rw-r--r-- | arch/x86/Kconfig.debug | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index e46c214..b322f12 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -129,6 +129,25 @@ config DOUBLEFAULT option saves about 4k and might cause you much additional grey hair. +config DEBUG_TLBFLUSH + bool "Set upper limit of TLB entries to flush one-by-one" + depends on DEBUG_KERNEL && (X86_64 || X86_INVLPG) + ---help--- + + X86-only for now. + + This option allows the user to tune the amount of TLB entries the + kernel flushes one-by-one instead of doing a full TLB flush. In + certain situations, the former is cheaper. This is controlled by the + tlb_flushall_shift knob under /sys/kernel/debug/x86. If you set it + to -1, the code flushes the whole TLB unconditionally. Otherwise, + for positive values of it, the kernel will use single TLB entry + invalidating instructions according to the following formula: + + flush_entries <= active_tlb_entries / 2^tlb_flushall_shift + + If in doubt, say "N". + config IOMMU_DEBUG bool "Enable IOMMU debugging" depends on GART_IOMMU && DEBUG_KERNEL |