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| author | Borislav Petkov <borislav.petkov@amd.com> | 2010-02-18 19:37:14 +0100 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2010-02-18 21:59:07 -0800 |
| commit | cb19060abfdecac0d1eb2d2f0e7d6b7a3f8bc4f4 (patch) | |
| tree | 994491932034c4b6be2a1c08d4098899c80aff8e /arch/x86/lib | |
| parent | f619b3d8427eb57f0134dab75b0d217325c72411 (diff) | |
| download | kernel_goldelico_gta04-cb19060abfdecac0d1eb2d2f0e7d6b7a3f8bc4f4.zip kernel_goldelico_gta04-cb19060abfdecac0d1eb2d2f0e7d6b7a3f8bc4f4.tar.gz kernel_goldelico_gta04-cb19060abfdecac0d1eb2d2f0e7d6b7a3f8bc4f4.tar.bz2 | |
x86, cacheinfo: Enable L3 CID only on AMD
Final stage linking can fail with
arch/x86/built-in.o: In function `store_cache_disable':
intel_cacheinfo.c:(.text+0xc509): undefined reference to `amd_get_nb_id'
arch/x86/built-in.o: In function `show_cache_disable':
intel_cacheinfo.c:(.text+0xc7d3): undefined reference to `amd_get_nb_id'
when CONFIG_CPU_SUP_AMD is not enabled because the amd_get_nb_id
helper is defined in AMD-specific code but also used in generic code
(intel_cacheinfo.c). Reorganize the L3 cache index disable code under
CONFIG_CPU_SUP_AMD since it is AMD-only anyway.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <20100218184210.GF20473@aftab>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/lib')
0 files changed, 0 insertions, 0 deletions