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| author | Ulrich Drepper <drepper@gmail.com> | 2012-01-17 14:14:02 -0500 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2012-01-17 12:11:54 -0800 |
| commit | ce79dac861e0d9a473d9923391bdbaad83c1c57f (patch) | |
| tree | 16c2b6fa5a167e3270de80719c14eb9bbe69b1ed /arch/x86 | |
| parent | 5ee71535440f034de1196b11f78cef81c4025c2b (diff) | |
| download | kernel_goldelico_gta04-ce79dac861e0d9a473d9923391bdbaad83c1c57f.zip kernel_goldelico_gta04-ce79dac861e0d9a473d9923391bdbaad83c1c57f.tar.gz kernel_goldelico_gta04-ce79dac861e0d9a473d9923391bdbaad83c1c57f.tar.bz2 | |
x86, opcode: ANDN and Group 17 in x86-opcode-map.txt
The Intel documentation at
http://software.intel.com/file/36945
shows the ANDN opcode and Group 17 with encoding f2 and f3 encoding
respectively. The current version of x86-opcode-map.txt shows them
with f3 and f4. Unless someone can point to documentation which shows
the currently used encoding the following patch be applied.
Signed-off-by: Ulrich Drepper <drepper@gmail.com>
Link: http://lkml.kernel.org/r/CAOPLpQdq5SuVo9=023CYhbFLAX9rONyjmYq7jJkqc5xwctW5eA@mail.gmail.com
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/lib/x86-opcode-map.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index 5b83c51..4c8010d 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -729,8 +729,8 @@ de: VAESDEC Vdq,Hdq,Wdq (66),(v1) df: VAESDECLAST Vdq,Hdq,Wdq (66),(v1) f0: MOVBE Gy,My | MOVBE Gw,Mw (66) | CRC32 Gd,Eb (F2) f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) -f3: ANDN Gy,By,Ey (v) -f4: Grp17 (1A) +f2: ANDN Gy,By,Ey (v) +f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) f6: MULX By,Gy,rDX,Ey (F2),(v) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v) |