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| author | Chris Zankel <chris@zankel.net> | 2008-02-12 10:11:45 -0800 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2008-02-13 17:08:18 -0800 |
| commit | 0b2c3afdaaaa3e577300b2235df43eb8af00020b (patch) | |
| tree | a19e12791a9d109f61f1edce731f50589302d04d /arch/xtensa/mm | |
| parent | 70e137eb48f62e59dfa5e06d0d01f123e9464f9a (diff) | |
| download | kernel_goldelico_gta04-0b2c3afdaaaa3e577300b2235df43eb8af00020b.zip kernel_goldelico_gta04-0b2c3afdaaaa3e577300b2235df43eb8af00020b.tar.gz kernel_goldelico_gta04-0b2c3afdaaaa3e577300b2235df43eb8af00020b.tar.bz2 | |
[XTENSA] Fix icache flush for cache aliasing
Set the execution bit in the temporary TLB when we flush the
instruction cache.
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/mm')
| -rw-r--r-- | arch/xtensa/mm/misc.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S index e1f8803..c885664 100644 --- a/arch/xtensa/mm/misc.S +++ b/arch/xtensa/mm/misc.S @@ -295,7 +295,7 @@ ENTRY(__tlbtemp_mapping_itlb) ENTRY(__invalidate_icache_page_alias) entry sp, 16 - addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) + addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE) mov a4, a2 witlb a6, a2 isync |