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| author | Marcelo Tosatti <marcelo@kvack.org> | 2006-05-05 17:09:29 -0300 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-05-09 16:03:11 +1000 |
| commit | c51e078f82096a7d35ac8ec2416272e843a0e1c4 (patch) | |
| tree | 211fa222b7f32a6ca08624c2e32c6b5d2c89ded5 /arch | |
| parent | e4de00215c3af02116db3d486bf53700dfe10619 (diff) | |
| download | kernel_goldelico_gta04-c51e078f82096a7d35ac8ec2416272e843a0e1c4.zip kernel_goldelico_gta04-c51e078f82096a7d35ac8ec2416272e843a0e1c4.tar.gz kernel_goldelico_gta04-c51e078f82096a7d35ac8ec2416272e843a0e1c4.tar.bz2 | |
[PATCH] ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation
Instantiation of 8MB pages on the TLB cache for the kernel static
mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations.
This ensures r3 gets saved and restored.
Signed-off-by: Marcelo Tosatti <marcelo@kvack.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/ppc/kernel/head_8xx.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index ec53c7d..7a2f205 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -355,9 +355,7 @@ InstructionTLBMiss: . = 0x1200 DataStoreTLBMiss: -#ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) -#endif DO_8xx_CPU6(0x3f80, r3) mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ mfcr r10 @@ -417,9 +415,7 @@ DataStoreTLBMiss: lwz r11, 0(r0) mtcr r11 lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is an instruction TLB error on the MPC8xx. This could be due |