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| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:42:53 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:42:53 -0700 |
| commit | 83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7 (patch) | |
| tree | bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce /crypto/async_tx/async_xor.c | |
| parent | 9308add6ea4fedeba37b0d7c4630a542bd34f214 (diff) | |
| download | kernel_goldelico_gta04-83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7.zip kernel_goldelico_gta04-83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7.tar.gz kernel_goldelico_gta04-83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7.tar.bz2 | |
dmaengine, async_tx: support alignment checks
Some engines have transfer size and address alignment restrictions. Add
a per-operation alignment property to struct dma_device that the async
routines and dmatest can use to check alignment capabilities.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'crypto/async_tx/async_xor.c')
| -rw-r--r-- | crypto/async_tx/async_xor.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index db27987..b459a90 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -193,7 +193,7 @@ async_xor(struct page *dest, struct page **src_list, unsigned int offset, else if (sizeof(dma_addr_t) <= sizeof(struct page *)) dma_src = (dma_addr_t *) src_list; - if (dma_src && chan) { + if (dma_src && chan && is_dma_xor_aligned(chan->device, offset, 0, len)) { /* run the xor asynchronously */ pr_debug("%s (async): len: %zu\n", __func__, len); @@ -265,7 +265,8 @@ async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, else if (sizeof(dma_addr_t) <= sizeof(struct page *)) dma_src = (dma_addr_t *) src_list; - if (dma_src && device && src_cnt <= device->max_xor) { + if (dma_src && device && src_cnt <= device->max_xor && + is_dma_xor_aligned(device, offset, 0, len)) { unsigned long dma_prep_flags = 0; int i; |