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| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-06-05 16:37:17 +0300 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-06-11 17:07:39 -0700 |
| commit | c388eee21ad20929f440d6fae94c995791c5818b (patch) | |
| tree | 2ed5b4f6dac099a401c38f0dbd68db26009c7b9b /drivers/clk | |
| parent | 053b525f6f0ef59ac905f0d2e38d39296f8e4fa6 (diff) | |
| download | kernel_goldelico_gta04-c388eee21ad20929f440d6fae94c995791c5818b.zip kernel_goldelico_gta04-c388eee21ad20929f440d6fae94c995791c5818b.tar.gz kernel_goldelico_gta04-c388eee21ad20929f440d6fae94c995791c5818b.tar.bz2 | |
clk: tegra: pllp_out2 divider is int only
The pllp_out2 should be integer only, the fractional bit should always be 0.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 797e58f..2dd9b00 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1200,8 +1200,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base, /* PLLP_OUT2 */ clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | - TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, - &pll_div_lock); + TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24, + 8, 1, &pll_div_lock); clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", clk_base + PLLP_OUTA, 17, 16, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, |