diff options
| author | Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> | 2013-08-24 10:47:48 -0500 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2013-08-27 15:00:22 +0200 |
| commit | 4fc06b3171f4de92cd21bf7ab1cb0bf62f05769d (patch) | |
| tree | 9f95e7ce272ba34b68d19c6fb42798e3c04c1863 /drivers/edac | |
| parent | 3f0aba4fc0ec789634c29a8265b90b8b0d1a4e29 (diff) | |
| download | kernel_goldelico_gta04-4fc06b3171f4de92cd21bf7ab1cb0bf62f05769d.zip kernel_goldelico_gta04-4fc06b3171f4de92cd21bf7ab1cb0bf62f05769d.tar.gz kernel_goldelico_gta04-4fc06b3171f4de92cd21bf7ab1cb0bf62f05769d.tar.bz2 | |
amd64_edac: Fix incorrect wraparounds
dct_base and dct_limit obtain 32 bit register values when they read
their respective pci config space registers. A left shift beyond 32 bits
will cause them to wrap around. Similar case for chan_addr as can be
seen from the bug report (link below). In the patch, we rectify this by
casting chan_addr to u64 and by comparing dct_base and dct_limit against
properly shifted sys_addr in order to compare the correct bits.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Link: http://lkml.kernel.org/r/20130819132302.GA12171@elgon.mountain
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/amd64_edac.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 6952d43..3c9e4e9 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1558,11 +1558,12 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, } /* Verify sys_addr is within DCT Range. */ - dct_base = (dct_sel_baseaddr(pvt) << 27); - dct_limit = (((dct_cont_limit_reg >> 11) & 0x1FFF) << 27) | 0x7FFFFFF; + dct_base = (u64) dct_sel_baseaddr(pvt); + dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF; if (!(dct_cont_base_reg & BIT(0)) && - !(dct_base <= sys_addr && dct_limit >= sys_addr)) + !(dct_base <= (sys_addr >> 27) && + dct_limit >= (sys_addr >> 27))) return -EINVAL; /* Verify number of dct's that participate in channel interleaving. */ @@ -1584,7 +1585,7 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, if (leg_mmio_hole && (sys_addr >= BIT_64(32))) chan_offset = dhar_offset; else - chan_offset = dct_base; + chan_offset = dct_base << 27; chan_addr = sys_addr - chan_offset; @@ -1614,7 +1615,7 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, amd64_read_pci_cfg(pvt->F1, DRAM_CONT_HIGH_OFF + (int) channel * 4, &tmp); - chan_addr += ((tmp >> 11) & 0xfff) << 27; + chan_addr += (u64) ((tmp >> 11) & 0xfff) << 27; } f15h_select_dct(pvt, channel); |