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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2013-08-26 16:18:54 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-09-03 11:10:55 +0200 |
| commit | 97e4eed7dc532e20208b0bdf7ad1136569da2f35 (patch) | |
| tree | f39dabaa2d93d05e8492bc8f78ced8ede4f70e0d /drivers/gpu/drm/udl | |
| parent | 521198a2e7095c8c7daa8d7d3a76a110c346be6f (diff) | |
| download | kernel_goldelico_gta04-97e4eed7dc532e20208b0bdf7ad1136569da2f35.zip kernel_goldelico_gta04-97e4eed7dc532e20208b0bdf7ad1136569da2f35.tar.gz kernel_goldelico_gta04-97e4eed7dc532e20208b0bdf7ad1136569da2f35.tar.bz2 | |
drm/i915: Adjust available RPS information through sysfs for vlv
Valleyview has its own render power state implementation with different
capability knobs - it has no RP0,RP1,RPn but rather RPe.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67734
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: kobe.qin@intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/udl')
0 files changed, 0 insertions, 0 deletions