diff options
| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-04-22 20:33:40 +0200 |
|---|---|---|
| committer | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-04-22 20:33:40 +0200 |
| commit | db2f38c22ea3f545be3b5772e5f9dc5861b74536 (patch) | |
| tree | 57b07f93fb6e474761a31446c96a9821e1aa98d8 /drivers/ide | |
| parent | 15da90b516e9da92cc1d90001e640fd6707d0e27 (diff) | |
| download | kernel_goldelico_gta04-db2f38c22ea3f545be3b5772e5f9dc5861b74536.zip kernel_goldelico_gta04-db2f38c22ea3f545be3b5772e5f9dc5861b74536.tar.gz kernel_goldelico_gta04-db2f38c22ea3f545be3b5772e5f9dc5861b74536.tar.bz2 | |
palm_bk3710: UDMA performance fix
Fix UDMA throughput bug: tCYC averages t2CYCTYP/2, but the code
previously assumed it was the same as t2CYCTYP. (That is, it was
using just one clock edge, not both.) Move the table's type
declaration so it's adjacent to the table, making it more clear
what those numbers mean.
On one system this change increased throughput by almost 4x: UDMA/66
sometimes topped 23 MB/sec (on a drive known to do much better). On
another system it was around a 10% win (UDMA/66 up to 7+ MB/sec).
The difference might be caused by the ratio between memory and IDE
clocks. In the system with large speedup, this was exactly 2 (as a
workaround for a rev 1.1 silicon bug). The other system used a more
standard ratio of 1.63 (and rev 2.1 silicon) ... clock domain synch
might have some issues, they're not unheard-of.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide')
| -rw-r--r-- | drivers/ide/palm_bk3710.c | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/drivers/ide/palm_bk3710.c b/drivers/ide/palm_bk3710.c index c7acca0..d1513b4 100644 --- a/drivers/ide/palm_bk3710.c +++ b/drivers/ide/palm_bk3710.c @@ -39,14 +39,6 @@ /* Primary Control Offset */ #define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6 -/* - * PalmChip 3710 IDE Controller UDMA timing structure Definition - */ -struct palm_bk3710_udmatiming { - unsigned int rptime; /* Ready to pause time */ - unsigned int cycletime; /* Cycle Time */ -}; - #define BK3710_BMICP 0x00 #define BK3710_BMISP 0x02 #define BK3710_BMIDTP 0x04 @@ -75,13 +67,19 @@ struct palm_bk3710_udmatiming { static unsigned ideclk_period; /* in nanoseconds */ +struct palm_bk3710_udmatiming { + unsigned int rptime; /* tRP -- Ready to pause time (nsec) */ + unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */ + /* tENV is always a minimum of 20 nsec */ +}; + static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = { - {160, 240}, /* UDMA Mode 0 */ - {125, 160}, /* UDMA Mode 1 */ - {100, 120}, /* UDMA Mode 2 */ - {100, 90}, /* UDMA Mode 3 */ - {100, 60}, /* UDMA Mode 4 */ - {85, 40}, /* UDMA Mode 5 */ + {160, 240 / 2,}, /* UDMA Mode 0 */ + {125, 160 / 2,}, /* UDMA Mode 1 */ + {100, 120 / 2,}, /* UDMA Mode 2 */ + {100, 90 / 2,}, /* UDMA Mode 3 */ + {100, 60 / 2,}, /* UDMA Mode 4 */ + {85, 40 / 2,}, /* UDMA Mode 5 */ }; static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, |