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| author | Guennadi Liakhovetski <g.liakhovetski@gmx.de> | 2012-01-04 15:34:17 +0100 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@linux.intel.com> | 2012-01-06 11:40:11 +0530 |
| commit | c11b46c32c8a9bf05fdb76d70d8dc74fcbfd02d1 (patch) | |
| tree | 970a85e6a577d878c5ee57f31a1ee3df0fb8ad00 /drivers/misc | |
| parent | f69f2e264f6388df6d3cae45dd67ddfd52aaa14b (diff) | |
| download | kernel_goldelico_gta04-c11b46c32c8a9bf05fdb76d70d8dc74fcbfd02d1.zip kernel_goldelico_gta04-c11b46c32c8a9bf05fdb76d70d8dc74fcbfd02d1.tar.gz kernel_goldelico_gta04-c11b46c32c8a9bf05fdb76d70d8dc74fcbfd02d1.tar.bz2 | |
dma: shdma: fix runtime PM: clear channel buffers on reset
On platforms, supporting power domains, if the domain, containing a DMAC
instance is powered down, the driver fails to resume correctly. On those
platforms DMAC channels have an additional CHCLR register for clearing
channel buffers. Using this register during runtime resume fixes the
problem.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Diffstat (limited to 'drivers/misc')
0 files changed, 0 insertions, 0 deletions