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| author | Stephen Hemminger <shemminger@vyatta.com> | 2010-04-24 20:04:12 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-04-24 20:04:12 -0700 |
| commit | bf73130d7f98c8c4db143e2dc4982f4eefd5d5e5 (patch) | |
| tree | 19a73b4ce836c4a7224706de5febb77ab1ca0c7f /drivers/net/sky2.h | |
| parent | b7d6a4321195c32b548f0185a2fa0b8f6e02bcfc (diff) | |
| download | kernel_goldelico_gta04-bf73130d7f98c8c4db143e2dc4982f4eefd5d5e5.zip kernel_goldelico_gta04-bf73130d7f98c8c4db143e2dc4982f4eefd5d5e5.tar.gz kernel_goldelico_gta04-bf73130d7f98c8c4db143e2dc4982f4eefd5d5e5.tar.bz2 | |
sky2: add support for receive hashing
Sky2 hardware supports hardware receive hash calculation.
Now that Receive Packet Steering is available, add support
to enable it.
This version does not depend on CONFIG_RPS. Also set_flags rejects
all values except RXHASH, so driver won't have to change next time
somebody adds a new one.
Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sky2.h')
| -rw-r--r-- | drivers/net/sky2.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 125b5bd..545a3f4 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h @@ -694,8 +694,21 @@ enum { TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ + + RSS_KEY = 0x0220, /* RSS Key setup */ + RSS_CFG = 0x0248, /* RSS Configuration */ }; +enum { + HASH_TCP_IPV6_EX_CTRL = 1<<5, + HASH_IPV6_EX_CTRL = 1<<4, + HASH_TCP_IPV6_CTRL = 1<<3, + HASH_IPV6_CTRL = 1<<2, + HASH_TCP_IPV4_CTRL = 1<<1, + HASH_IPV4_CTRL = 1<<0, + + HASH_ALL = 0x3f, +}; enum { B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ @@ -2261,6 +2274,7 @@ struct sky2_hw { #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */ #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */ #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */ +#define SKY2_HW_RSS_BROKEN 0x00000100 u8 chip_id; u8 chip_rev; |