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| author | Ivo van Doorn <ivdoorn@gmail.com> | 2008-08-04 16:38:02 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2008-08-22 16:29:58 -0400 |
| commit | 61e754f44b57060464b1fcf261a8428ecfa23bed (patch) | |
| tree | 0fab4e6777f4ad317dac446d0afb24efb9257636 /drivers/net/wireless/rt2x00/rt61pci.h | |
| parent | 2bb057d07a0bc17475a7bf897fc41667ab08b73f (diff) | |
| download | kernel_goldelico_gta04-61e754f44b57060464b1fcf261a8428ecfa23bed.zip kernel_goldelico_gta04-61e754f44b57060464b1fcf261a8428ecfa23bed.tar.gz kernel_goldelico_gta04-61e754f44b57060464b1fcf261a8428ecfa23bed.tar.bz2 | |
rt2x00: Implement HW encryption (rt61pci)
rt61pci supports hardware encryption.
rt61pci supports up to 4 shared keys and up to 64 pairwise keys.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.h')
| -rw-r--r-- | drivers/net/wireless/rt2x00/rt61pci.h | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.h b/drivers/net/wireless/rt2x00/rt61pci.h index 1004d5b..6d591ce 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.h +++ b/drivers/net/wireless/rt2x00/rt61pci.h @@ -134,6 +134,16 @@ #define PAIRWISE_KEY_TABLE_BASE 0x1200 #define PAIRWISE_TA_TABLE_BASE 0x1a00 +#define SHARED_KEY_ENTRY(__idx) \ + ( SHARED_KEY_TABLE_BASE + \ + ((__idx) * sizeof(struct hw_key_entry)) ) +#define PAIRWISE_KEY_ENTRY(__idx) \ + ( PAIRWISE_KEY_TABLE_BASE + \ + ((__idx) * sizeof(struct hw_key_entry)) ) +#define PAIRWISE_TA_ENTRY(__idx) \ + ( PAIRWISE_TA_TABLE_BASE + \ + ((__idx) * sizeof(struct hw_pairwise_ta_entry)) ) + struct hw_key_entry { u8 key[16]; u8 tx_mic[8]; @@ -142,7 +152,8 @@ struct hw_key_entry { struct hw_pairwise_ta_entry { u8 address[6]; - u8 reserved[2]; + u8 cipher; + u8 reserved; } __attribute__ ((packed)); /* @@ -662,6 +673,10 @@ struct hw_pairwise_ta_entry { * SEC_CSR4: Pairwise key table lookup control. */ #define SEC_CSR4 0x30b0 +#define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001) +#define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002) +#define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004) +#define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008) /* * SEC_CSR5: shared key table security mode register. @@ -1428,8 +1443,10 @@ struct hw_pairwise_ta_entry { /* * Word4 + * ICV: Received ICV of originally encrypted. + * NOTE: This is a guess, the official definition is "reserved" */ -#define RXD_W4_RESERVED FIELD32(0xffffffff) +#define RXD_W4_ICV FIELD32(0xffffffff) /* * the above 20-byte is called RXINFO and will be DMAed to MAC RX block |