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| author | Bjorn Helgaas <bhelgaas@google.com> | 2013-08-28 12:01:03 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-08-28 20:51:39 -0600 |
| commit | 6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e (patch) | |
| tree | 07479c9db0957162e0b4c7a80be46361152a6838 /drivers/pci | |
| parent | c8b303d0206b28c4ff3aecada47108d1655ae00f (diff) | |
| download | kernel_goldelico_gta04-6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e.zip kernel_goldelico_gta04-6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e.tar.gz kernel_goldelico_gta04-6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e.tar.bz2 | |
PCI: Support PCIe Capability Slot registers only for ports with slots
Previously we allowed callers to access Slot Capabilities, Status, and
Control for Root Ports even if the Root Port did not implement a slot.
This seems dubious because the spec only requires these registers if a
slot is implemented.
It's true that even Root Ports without slots must have *space* for these
slot registers, because the Root Capabilities, Status, and Control
registers are after the slot registers in the capability. However,
for a v1 PCIe Capability, the *semantics* of the slot registers are
undefined unless a slot is implemented.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-By: Jiang Liu <jiang.liu@huawei.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/access.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/access.c b/drivers/pci/access.c index 9a46fa9..061da8c 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -497,9 +497,9 @@ static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) { int type = pci_pcie_type(dev); - return type == PCI_EXP_TYPE_ROOT_PORT || - (type == PCI_EXP_TYPE_DOWNSTREAM && - pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT); + return (type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_DOWNSTREAM) && + pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; } static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) |