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authorJason Wang <jason77.wang@gmail.com>2010-10-19 18:03:27 +0800
committerGrant Likely <grant.likely@secretlab.ca>2010-10-20 10:30:53 -0600
commite1993ed6420afd4421336d75e73641f75da87a7f (patch)
treec511d2aabbf7107620123954757df7bf7264c404 /drivers/spi
parentdb181a8ee158fd0ccea2e2670c4f2d36af2814a0 (diff)
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spi/omap2_mcspi: disable channel after TX_ONLY transfer in PIO mode
In the TX_ONLY transfer, the SPI controller also receives data simultaneously and saves them in the rx register. After the TX_ONLY transfer, the rx register will hold the random data received during the last tx transaction. If the direct following transfer is RX_ONLY, this random data has the possibility to affect this transfer like this: When the SPI controller is changed from TX_ONLY to RX_ONLY, the random data makes the rx register full immediately and triggers a dummy write automatically(in SPI RX_ONLY transfers, we need a dummy write to trigger the first transaction). So the first data received in the RX_ONLY transfer will be that random data instead of something meaningful. We can avoid this by inserting a Disable/Re-enable toggle of the channel after the TX_ONLY transfer, since it purges the rx register. Signed-off-by: Jason Wang <jason77.wang@gmail.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/omap2_mcspi.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index d703927..27a3fa1 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -626,6 +626,12 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
} else if (mcspi_wait_for_reg_bit(chstat_reg,
OMAP2_MCSPI_CHSTAT_EOT) < 0)
dev_err(&spi->dev, "EOT timed out\n");
+
+ /* disable chan to purge rx datas received in TX_ONLY transfer,
+ * otherwise these rx datas will affect the direct following
+ * RX_ONLY transfer.
+ */
+ omap2_mcspi_set_enable(spi, 0);
}
out:
omap2_mcspi_set_enable(spi, 1);