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| author | Seth Heasley <seth.heasley@intel.com> | 2012-05-22 22:54:20 +0200 |
|---|---|---|
| committer | Samuel Ortiz <sameo@linux.intel.com> | 2012-05-22 23:39:14 +0200 |
| commit | 77820ffae678fa7ff6cc155354825b6b1a023afb (patch) | |
| tree | 8bc685ea2a3a867042c2537b04cce2c48cf597bb /drivers | |
| parent | 1fe17a24e2fe0a9554d19a4249eb2d80050ecb8c (diff) | |
| download | kernel_goldelico_gta04-77820ffae678fa7ff6cc155354825b6b1a023afb.zip kernel_goldelico_gta04-77820ffae678fa7ff6cc155354825b6b1a023afb.tar.gz kernel_goldelico_gta04-77820ffae678fa7ff6cc155354825b6b1a023afb.tar.bz2 | |
gpio: Add Intel Centerton support to gpio-sch
This patch adds the Intel Centerton processor device ID for GPIO.
The device ID is defined in include/linux/pci_ids.h
Signed-off-by: Seth Heasley <seth.heasley@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpio/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/gpio/gpio-sch.c | 8 |
2 files changed, 14 insertions, 3 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 09ac540..6da36a5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -170,13 +170,13 @@ config GPIO_VR41XX Say yes here to support the NEC VR4100 series General-purpose I/O Uint config GPIO_SCH - tristate "Intel SCH/TunnelCreek GPIO" + tristate "Intel SCH/TunnelCreek/Centerton GPIO" depends on PCI && X86 select MFD_CORE select LPC_SCH help - Say yes here to support GPIO interface on Intel Poulsbo SCH - or Intel Tunnel Creek processor. + Say yes here to support GPIO interface on Intel Poulsbo SCH, + Intel Tunnel Creek processor or Intel Centerton processor. The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are powered by the core power rail and are turned off during sleep modes (S3 and higher). The remaining four GPIOs are powered by @@ -185,6 +185,9 @@ config GPIO_SCH system from the Suspend-to-RAM state. The Intel Tunnel Creek processor has 5 GPIOs powered by the core power rail and 9 from suspend power supply. + The Intel Centerton processor has a total of 30 GPIO pins. + Twenty-one are powered by the core power rail and 9 from the + suspend power supply. config GPIO_ICH tristate "Intel ICH GPIO" diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c index 8cadf4d..424dce8 100644 --- a/drivers/gpio/gpio-sch.c +++ b/drivers/gpio/gpio-sch.c @@ -232,6 +232,14 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev) sch_gpio_resume.ngpio = 9; break; + case PCI_DEVICE_ID_INTEL_CENTERTON_ILB: + sch_gpio_core.base = 0; + sch_gpio_core.ngpio = 21; + + sch_gpio_resume.base = 21; + sch_gpio_resume.ngpio = 9; + break; + default: return -ENODEV; } |