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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-08-01 16:47:15 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-08-01 16:47:15 -0700 |
| commit | 1a9b4993b70fb1884716902774dc9025b457760d (patch) | |
| tree | 83a3fa7011878ab4b7bef6857d4b481038a1e67e /firmware/cxgb3 | |
| parent | 1871e845e564c4e17f561ec4e5e4bb6bb8578685 (diff) | |
| parent | 95cf1468f712df516cc471adcd1c861df4e3d371 (diff) | |
| download | kernel_goldelico_gta04-1a9b4993b70fb1884716902774dc9025b457760d.zip kernel_goldelico_gta04-1a9b4993b70fb1884716902774dc9025b457760d.tar.gz kernel_goldelico_gta04-1a9b4993b70fb1884716902774dc9025b457760d.tar.bz2 | |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"The lion share of this pull request are fixes for clk-related breakage
caused by other changes during this merge window. For some platforms
the fix was as simple as selecting HAVE_CLK, for others like the
Loongson 2 significant restructuring was required.
The remainder are changes required to get the Lantiq code to work
again."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Loongson 2: Sort out clock managment.
MIPS: Loongson 1: more clk support and add select HAVE_CLK
MIPS: txx9: Fix redefinition of clk_* by adding select HAVE_CLK
MIPS: BCM63xx: Fix redefinition of clk_* by adding select HAVE_CLK
MIPS: AR7: Fix redefinition of clk_* by adding select HAVE_CLK
MIPS: Lantiq: Platform specific CLK fixup
MIPS: Lantiq: Add device_tree_init function
MIPS: Lantiq: Fix interface clock and PCI control register offset
Diffstat (limited to 'firmware/cxgb3')
0 files changed, 0 insertions, 0 deletions