diff options
| author | Ben Nizette <ben@mallochdigital.com> | 2006-10-24 10:12:43 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-10-25 20:26:33 -0700 |
| commit | 065834ab3988fece5608088e83724891c8190a2f (patch) | |
| tree | 53f4f4abf61ea228c2a78ca7de9e44642ab3c124 /include/asm-avr32 | |
| parent | fa3522407f01ead1ec14bdd6b785ea08d17d500d (diff) | |
| download | kernel_goldelico_gta04-065834ab3988fece5608088e83724891c8190a2f.zip kernel_goldelico_gta04-065834ab3988fece5608088e83724891c8190a2f.tar.gz kernel_goldelico_gta04-065834ab3988fece5608088e83724891c8190a2f.tar.bz2 | |
[PATCH] AVR32: add io{read,write}{8,16,32}{be,} support
A number of new drivers require io{read,write}{8,16,32}{be,} family of io
operations. These are provided for the AVR32 by this patch in the form of
a series of macros.
Access to the (memory mapped) io space through these macros is defined to
be little endian only as little endian devices (such as PCI) are the main
consumer of IO access. If high speed access is required,
io{read,write}{16,32}be macros are supplied to perform native big endian
access to this io space.
Signed-off-by: Ben Nizette <ben@mallochdigital.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-avr32')
| -rw-r--r-- | include/asm-avr32/io.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index 2fc8f11..eec4750 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -76,6 +76,39 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define readsw(p, d, l) __raw_readsw((unsigned int)p, d, l) #define readsl(p, d, l) __raw_readsl((unsigned int)p, d, l) + +/* + * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be + */ +#ifndef ioread8 + +#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) + +#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; }) +#define ioread16be(p) ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; }) + +#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; }) +#define ioread32be(p) ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; }) + +#define iowrite8(v,p) __raw_writeb(v, p) + +#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p) +#define iowrite16be(v,p) __raw_writew(cpu_to_be16(v), p) + +#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p) +#define iowrite32be(v,p) __raw_writel(cpu_to_be32(v), p) + +#define ioread8_rep(p,d,c) __raw_readsb(p,d,c) +#define ioread16_rep(p,d,c) __raw_readsw(p,d,c) +#define ioread32_rep(p,d,c) __raw_readsl(p,d,c) + +#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c) +#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c) +#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c) + +#endif + + /* * These two are only here because ALSA _thinks_ it needs them... */ |