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| author | Venki Pallipadi <venkatesh.pallipadi@intel.com> | 2008-01-30 13:32:01 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-01-30 13:32:01 +0100 |
| commit | bde6f5f59c2b2b48a7a849c129d5b48838fe77ee (patch) | |
| tree | 4fa3befdfa227db56770a0dc85b8fc18be232f70 /include/asm-ia64 | |
| parent | 7d409d6057c7244f8757ce15245f6df27271be0c (diff) | |
| download | kernel_goldelico_gta04-bde6f5f59c2b2b48a7a849c129d5b48838fe77ee.zip kernel_goldelico_gta04-bde6f5f59c2b2b48a7a849c129d5b48838fe77ee.tar.gz kernel_goldelico_gta04-bde6f5f59c2b2b48a7a849c129d5b48838fe77ee.tar.bz2 | |
x86: voluntary leave_mm before entering ACPI C3
Aviod TLB flush IPIs during C3 states by voluntary leave_mm()
before entering C3.
The performance impact of TLB flush on C3 should not be significant with
respect to C3 wakeup latency. Also, CPUs tend to flush TLB in hardware while in
C3 anyways.
On a 8 logical CPU system, running make -j2, the number of tlbflush IPIs goes
down from 40 per second to ~ 0. Total number of interrupts during the run
of this workload was ~1200 per second, which makes it ~3% savings in wakeups.
There was no measurable performance or power impact however.
[ akpm@linux-foundation.org: symbol export fixes. ]
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/asm-ia64')
| -rw-r--r-- | include/asm-ia64/acpi.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h index 81bcd5e..cd1cc39 100644 --- a/include/asm-ia64/acpi.h +++ b/include/asm-ia64/acpi.h @@ -127,6 +127,8 @@ extern int __devinitdata pxm_to_nid_map[MAX_PXM_DOMAINS]; extern int __initdata nid_to_pxm_map[MAX_NUMNODES]; #endif +#define acpi_unlazy_tlb(x) + #endif /*__KERNEL__*/ #endif /*_ASM_ACPI_H*/ |