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author | Paul Mundt <lethal@linux-sh.org> | 2007-12-10 15:50:28 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-28 13:18:59 +0900 |
commit | cd01204b82933754a7276838656420477f64d4b8 (patch) | |
tree | f9e3b11574bec04cda78c549cdc5c37c3c75c4a5 /include/asm-sh/system.h | |
parent | c8c0a1aba9fa8f816dc8fb477ff816a5b700f0ea (diff) | |
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sh: Encode L1/L2 cache shape in auxvt.
This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace libc side for calculating a tightly packed
SHMLBA amongst other things.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/system.h')
-rw-r--r-- | include/asm-sh/system.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h index 9bda8d0..8459255 100644 --- a/include/asm-sh/system.h +++ b/include/asm-sh/system.h @@ -12,7 +12,7 @@ #include <asm/types.h> #include <asm/ptrace.h> -#define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */ +#define AT_VECTOR_SIZE_ARCH 4 /* entries in ARCH_DLINFO */ #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5) #define __icbi() \ |