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| author | David S. Miller <davem@davemloft.net> | 2006-01-31 18:31:20 -0800 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 01:11:17 -0800 |
| commit | 98c5584cfc47932c4f3ccf5eee2e0bae1447b85e (patch) | |
| tree | c067ac8bfc081bbe0b3073374cb15708458e04ab /include/asm-sparc64/tsb.h | |
| parent | 09f94287f7260e03bbeab497e743691fafcc22c3 (diff) | |
| download | kernel_goldelico_gta04-98c5584cfc47932c4f3ccf5eee2e0bae1447b85e.zip kernel_goldelico_gta04-98c5584cfc47932c4f3ccf5eee2e0bae1447b85e.tar.gz kernel_goldelico_gta04-98c5584cfc47932c4f3ccf5eee2e0bae1447b85e.tar.bz2 | |
[SPARC64]: Add infrastructure for dynamic TSB sizing.
This also cleans up tsb_context_switch(). The assembler
routine is now __tsb_context_switch() and the former is
an inline function that picks out the bits from the mm_struct
and passes it into the assembler code as arguments.
setup_tsb_parms() computes the locked TLB entry to map the
TSB. Later when we support using the physical address quad
load instructions of Cheetah+ and later, we'll simply use
the physical address for the TSB register value and set
the map virtual and PTE both to zero.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/tsb.h')
| -rw-r--r-- | include/asm-sparc64/tsb.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-sparc64/tsb.h b/include/asm-sparc64/tsb.h index 03d272e..1f93b7d 100644 --- a/include/asm-sparc64/tsb.h +++ b/include/asm-sparc64/tsb.h @@ -19,7 +19,7 @@ * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN * retry * - + * * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu * register which is: |