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| author | Fabio Estevam <festevam@gmail.com> | 2013-06-28 00:23:09 -0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2013-06-28 12:56:04 +0200 |
| commit | d55f0cc4c9a70e3105f1e813ab5f221a65ac2ec3 (patch) | |
| tree | 64c7ebbb32548469c876494e5d334f310b2a3be8 /kernel/irq | |
| parent | 2779db8d37d4b542d9ca2575f5f178dbeaca6c86 (diff) | |
| download | kernel_goldelico_gta04-d55f0cc4c9a70e3105f1e813ab5f221a65ac2ec3.zip kernel_goldelico_gta04-d55f0cc4c9a70e3105f1e813ab5f221a65ac2ec3.tar.gz kernel_goldelico_gta04-d55f0cc4c9a70e3105f1e813ab5f221a65ac2ec3.tar.bz2 | |
genirq: generic-chip: Export some irq_gc_ functions
When building imx_v6_v7_defconfig with imx-drm drivers selected as
modules, we get the following build errors:
ERROR: "irq_gc_mask_clr_bit" [drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.ko] undefined!
ERROR: "irq_gc_mask_set_bit" [drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.ko] undefined!
ERROR: "irq_gc_ack_set_bit" [drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.ko] undefined!
Export the required functions to avoid this problem.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Cc: shawn.guo@linaro.org
Cc: kernel@pengutronix.de
Link: http://lkml.kernel.org/r/1372389789-7048-1-git-send-email-festevam@gmail.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'kernel/irq')
| -rw-r--r-- | kernel/irq/generic-chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index a746a8f..76ea748 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -62,6 +62,7 @@ void irq_gc_mask_set_bit(struct irq_data *d) irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } +EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit); /** * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register @@ -81,6 +82,7 @@ void irq_gc_mask_clr_bit(struct irq_data *d) irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); irq_gc_unlock(gc); } +EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit); /** * irq_gc_unmask_enable_reg - Unmask chip via enable register @@ -115,6 +117,7 @@ void irq_gc_ack_set_bit(struct irq_data *d) irq_reg_writel(mask, gc->reg_base + ct->regs.ack); irq_gc_unlock(gc); } +EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit); /** * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit |