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| author | David Henningsson <david.henningsson@canonical.com> | 2013-04-10 12:26:07 +0200 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2013-04-17 08:13:44 +0200 |
| commit | 83f26ad2c909083fa638d2df1b1a25bcbf2d1be2 (patch) | |
| tree | 87c8999c9e6dff6f0a922b8ba3795307fd8afd37 /sound/pci/hda | |
| parent | 5ead56f2dad53c6c2eaaf13e2de4125a59a3935b (diff) | |
| download | kernel_goldelico_gta04-83f26ad2c909083fa638d2df1b1a25bcbf2d1be2.zip kernel_goldelico_gta04-83f26ad2c909083fa638d2df1b1a25bcbf2d1be2.tar.gz kernel_goldelico_gta04-83f26ad2c909083fa638d2df1b1a25bcbf2d1be2.tar.bz2 | |
ALSA: hda - fixup D3 pin and right channel mute on Haswell HDMI audio
When graphics initializes the HDMI chip, sometimes this leads to
pins going into D3 and right channel being muted. If the audio driver
finishes initialization before the graphic driver does, this situation
becomes permanent.
This is a workaround that checks for this situation and corrects it on
playback prepare. It has been verified working on at least one machine.
BugLink: https://bugs.launchpad.net/bugs/1167270
Signed-off-by: David Henningsson <david.henningsson@canonical.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci/hda')
| -rw-r--r-- | sound/pci/hda/patch_hdmi.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index ede8215..32930e6 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -1018,6 +1018,41 @@ static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) hdmi_non_intrinsic_event(codec, res); } +static void haswell_verify_pin_D0(struct hda_codec *codec, hda_nid_t nid) +{ + int pwr, lamp, ramp; + + pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); + pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; + if (pwr != AC_PWRST_D0) { + snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, + AC_PWRST_D0); + msleep(40); + pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); + pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; + snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); + } + + lamp = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_AMP_GAIN_MUTE, + AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT); + ramp = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_AMP_GAIN_MUTE, + AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT); + if (lamp != ramp) { + snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_AMP_GAIN_MUTE, + AC_AMP_SET_RIGHT | AC_AMP_SET_OUTPUT | lamp); + + lamp = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_AMP_GAIN_MUTE, + AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT); + ramp = snd_hda_codec_read(codec, nid, 0, + AC_VERB_GET_AMP_GAIN_MUTE, + AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT); + snd_printd("Haswell HDMI audio: Mute after set on pin 0x%x: [0x%x 0x%x]\n", nid, lamp, ramp); + } +} + /* * Callbacks */ @@ -1032,6 +1067,9 @@ static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, int pinctl; int new_pinctl = 0; + if (codec->vendor_id == 0x80862807) + haswell_verify_pin_D0(codec, pin_nid); + if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { pinctl = snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |