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authorJorge Eduardo Candelaria <jorge.candelaria@ti.com>2010-05-20 17:53:07 -0500
committerLiam Girdwood <lrg@slimlogic.co.uk>2010-05-21 10:47:25 +0100
commit44ebaa5de1f922965d8aa215a6da729341b3deb2 (patch)
treec6691f48e549ce928f4fb673cc33405221dbd725 /sound/soc
parentad8332c1302bcb4f80d593fd3eb477be9d7f5604 (diff)
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ASoC: TWL6040: Fix playback with 19.2 Mhz MCLK
When using MCLK is configured for 19.2 Mhz, clock slicer should be enabled and HPPLL should be bypassed in clock path. Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ti.com> Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc')
-rw-r--r--sound/soc/codecs/twl6040.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index af36346..85dd4fb 100644
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -928,7 +928,7 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
case 19200000:
/* mclk input, pll disabled */
hppllctl |= TWL6040_MCLK_19200KHZ |
- TWL6040_HPLLSQRBP |
+ TWL6040_HPLLSQRENA |
TWL6040_HPLLBP;
break;
case 26000000: