diff options
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8610_hpcd.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8610_hpcd.dts | 93 |
1 files changed, 84 insertions, 9 deletions
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 1f2f1e0..fa9b6bb 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -21,6 +21,7 @@ serial1 = &serial1; pci0 = &pci0; pci1 = &pci1; + pci2 = &pci2; }; cpus { @@ -45,9 +46,63 @@ reg = <0x00000000 0x20000000>; // 512M at 0x0 }; - board-control@e8000000 { - compatible = "fsl,fpga-pixis"; - reg = <0xe8000000 32>; // pixis at 0xe8000000 + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + ranges = <0 0 0xf8000000 0x08000000 + 1 0 0xf0000000 0x08000000 + 2 0 0xe8400000 0x00008000 + 4 0 0xe8440000 0x00008000 + 5 0 0xe8480000 0x00008000 + 6 0 0xe84c0000 0x00008000 + 3 0 0xe8000000 0x00000020>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + flash@1,0 { + compatible = "cfi-flash"; + reg = <1 0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + flash@2,0 { + compatible = "fsl,mpc8610-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <2 0 0x8000>; + }; + + flash@4,0 { + compatible = "fsl,mpc8610-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <4 0 0x8000>; + }; + + flash@5,0 { + compatible = "fsl,mpc8610-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <5 0 0x8000>; + }; + + flash@6,0 { + compatible = "fsl,mpc8610-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <6 0 0x8000>; + }; + + board-control@3,0 { + compatible = "fsl,fpga-pixis"; + reg = <3 0 0x20>; + }; }; soc@e0000000 { @@ -105,7 +160,7 @@ compatible = "ns16550"; reg = <0x4600 0x100>; clock-frequency = <0>; - interrupts = <28 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -196,14 +251,14 @@ dma@c300 { #address-cells = <1>; #size-cells = <1>; - compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma"; + compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma"; cell-index = <1>; reg = <0xc300 0x4>; /* DMA general status register */ ranges = <0x0 0xc100 0x200>; dma-channel@0 { compatible = "fsl,mpc8610-dma-channel", - "fsl,mpc8540-dma-channel"; + "fsl,eloplus-dma-channel"; cell-index = <0>; reg = <0x0 0x80>; interrupt-parent = <&mpic>; @@ -211,7 +266,7 @@ }; dma-channel@1 { compatible = "fsl,mpc8610-dma-channel", - "fsl,mpc8540-dma-channel"; + "fsl,eloplus-dma-channel"; cell-index = <1>; reg = <0x80 0x80>; interrupt-parent = <&mpic>; @@ -219,7 +274,7 @@ }; dma-channel@2 { compatible = "fsl,mpc8610-dma-channel", - "fsl,mpc8540-dma-channel"; + "fsl,eloplus-dma-channel"; cell-index = <2>; reg = <0x100 0x80>; interrupt-parent = <&mpic>; @@ -227,7 +282,7 @@ }; dma-channel@3 { compatible = "fsl,mpc8610-dma-channel", - "fsl,mpc8540-dma-channel"; + "fsl,eloplus-dma-channel"; cell-index = <3>; reg = <0x180 0x80>; interrupt-parent = <&mpic>; @@ -322,4 +377,24 @@ }; }; }; + + pci2: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8641-pcie"; + reg = <0xe0009000 0x00001000>; + ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 + 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0000 0 0 1 &mpic 4 1 + 0x0000 0 0 2 &mpic 5 1 + 0x0000 0 0 3 &mpic 6 1 + 0x0000 0 0 4 &mpic 7 1>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + clock-frequency = <33333333>; + }; }; |