aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorjt1134 <jt1134@gmail.com>2012-10-23 21:26:34 -0500
committerjt1134 <jt1134@gmail.com>2012-10-23 21:26:34 -0500
commit615090c3ad1b061e78ae5ef685a63b72f79a7f60 (patch)
tree84f900f7d802cf418db46e246a50ece69438f07b
parente6a4849e8cc21f40233a0ab331897783be38637a (diff)
downloadkernel_samsung_aries-615090c3ad1b061e78ae5ef685a63b72f79a7f60.zip
kernel_samsung_aries-615090c3ad1b061e78ae5ef685a63b72f79a7f60.tar.gz
kernel_samsung_aries-615090c3ad1b061e78ae5ef685a63b72f79a7f60.tar.bz2
enable 1.2GHz OC
* keep same voltage settings as 1GHz * properly update APLL values * set max freq to 1GHz on bootup, up to the user to OC Change-Id: I643cb1b54dd684b9dbe6066fbdef1a86b9123d79
-rwxr-xr-xarch/arm/mach-s5pv210/cpufreq.c48
-rw-r--r--arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h2
-rw-r--r--arch/arm/mach-s5pv210/mach-aries.c4
3 files changed, 38 insertions, 16 deletions
diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c
index f1c0b77..1f3f9a5 100755
--- a/arch/arm/mach-s5pv210/cpufreq.c
+++ b/arch/arm/mach-s5pv210/cpufreq.c
@@ -32,7 +32,8 @@ static struct clk *dmc1_clk;
static struct cpufreq_freqs freqs;
static DEFINE_MUTEX(set_freq_lock);
-/* APLL M,P,S values for 1G/800Mhz */
+/* APLL M,P,S values for 1.2G/1G/800Mhz */
+#define APLL_VAL_1200 ((1 << 31) | (150 << 16) | (3 << 8) | 1)
#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
@@ -73,6 +74,7 @@ enum s5pv210_dmc_port {
};
static struct cpufreq_frequency_table s5pv210_freq_table[] = {
+ {OC0, 1200*1000},
{L0, 1000*1000},
{L1, 800*1000},
{L2, 400*1000},
@@ -100,6 +102,10 @@ const unsigned long arm_volt_max = 1350000;
const unsigned long int_volt_max = 1250000;
static struct s5pv210_dvs_conf dvs_conf[] = {
+ [OC0] = {
+ .arm_volt = 1275000,
+ .int_volt = 1100000,
+ },
[L0] = {
.arm_volt = 1275000,
.int_volt = 1100000,
@@ -122,7 +128,7 @@ static struct s5pv210_dvs_conf dvs_conf[] = {
},
};
-static u32 clkdiv_val[5][11] = {
+static u32 clkdiv_val[6][11] = {
/*
* Clock divider value for following
* { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
@@ -130,6 +136,9 @@ static u32 clkdiv_val[5][11] = {
* ONEDRAM, MFC, G3D }
*/
+ /* OC0 : [1200/200/100][166/83][133/66][200/200] */
+ {0, 5, 5, 1, 3, 1, 4, 1, 3, 0, 0},
+
/* L0 : [1000/200/100][166/83][133/66][200/200] */
{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
@@ -260,7 +269,7 @@ static int s5pv210_target(struct cpufreq_policy *policy,
unsigned int relation)
{
unsigned long reg;
- unsigned int index, priv_index;
+ unsigned int index;
unsigned int pll_changing = 0;
unsigned int bus_speed_changing = 0;
unsigned int arm_volt, int_volt;
@@ -303,13 +312,6 @@ static int s5pv210_target(struct cpufreq_policy *policy,
if (freqs.new == freqs.old)
goto out;
- /* Finding current running level index */
- if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
- freqs.old, relation, &priv_index)) {
- ret = -EINVAL;
- goto out;
- }
-
arm_volt = dvs_conf[index].arm_volt;
int_volt = dvs_conf[index].int_volt;
@@ -330,12 +332,15 @@ static int s5pv210_target(struct cpufreq_policy *policy,
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+ /* Don't use cpufreq_frequency_table_target() any more as it */
+ /* may not be accurate. Compare against freqs.old instead */
+
/* Check if there need to change PLL */
- if ((index == L0) || (priv_index == L0))
+ if ((index <= L0) || (freqs.old >= s5pv210_freq_table[L0].frequency))
pll_changing = 1;
/* Check if there need to change System bus clock */
- if ((index == L4) || (priv_index == L4))
+ if ((index == L4) || (freqs.old == s5pv210_freq_table[L4].frequency))
bus_speed_changing = 1;
if (bus_speed_changing) {
@@ -450,10 +455,17 @@ static int s5pv210_target(struct cpufreq_policy *policy,
* 6-1. Set PMS values
* 6-2. Wait untile the PLL is locked
*/
- if (index == L0)
+ switch (index) {
+ case OC0:
+ __raw_writel(APLL_VAL_1200, S5P_APLL_CON);
+ break;
+ case L0:
__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
- else
+ break;
+ default:
__raw_writel(APLL_VAL_800, S5P_APLL_CON);
+ break;
+ }
do {
reg = __raw_readl(S5P_APLL_CON);
@@ -584,6 +596,7 @@ static int check_mem_type(void __iomem *dmc_reg)
static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
{
unsigned long mem_type;
+ int ret;
cpu_clk = clk_get(NULL, "armclk");
if (IS_ERR(cpu_clk))
@@ -635,7 +648,12 @@ static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
g_dvfslockval[i] = MAX_PERF_LEVEL;
#endif
- return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
+ /* Set max freq to 1GHz on startup */
+ ret = cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
+ policy->min = 100000;
+ policy->max = 1000000;
+
+ return ret;
}
static int s5pv210_cpufreq_notifier_event(struct notifier_block *this,
diff --git a/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h
index 5add93a..4d4469a 100644
--- a/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h
+++ b/arch/arm/mach-s5pv210/include/mach/cpu-freq-v210.h
@@ -15,7 +15,7 @@
#include <linux/cpufreq.h>
enum perf_level {
- L0, L1, L2, L3, L4, MAX_PERF_LEVEL = L4,
+ OC0, L0, L1, L2, L3, L4, MAX_PERF_LEVEL = L4,
};
/* For cpu-freq driver */
diff --git a/arch/arm/mach-s5pv210/mach-aries.c b/arch/arm/mach-s5pv210/mach-aries.c
index f5d7757..15fff7c 100644
--- a/arch/arm/mach-s5pv210/mach-aries.c
+++ b/arch/arm/mach-s5pv210/mach-aries.c
@@ -412,6 +412,10 @@ static struct s5p_media_device aries_media_devs[] = {
#ifdef CONFIG_CPU_FREQ
static struct s5pv210_cpufreq_voltage smdkc110_cpufreq_volt[] = {
{
+ .freq = 1200000,
+ .varm = 1275000,
+ .vint = 1100000,
+ }, {
.freq = 1000000,
.varm = 1275000,
.vint = 1100000,