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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-01-04 15:09:29 -0800 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-19 12:35:27 +0000 |
| commit | 65993d64a31844ad444694efb2d159eb9c883e49 (patch) | |
| tree | 25be59baeff5c16726d0219a1d84d52c93df88bf | |
| parent | 01fe9dbde19a1a27b8ee63e2d964562962e1eb78 (diff) | |
| download | kernel_samsung_aries-65993d64a31844ad444694efb2d159eb9c883e49.zip kernel_samsung_aries-65993d64a31844ad444694efb2d159eb9c883e49.tar.gz kernel_samsung_aries-65993d64a31844ad444694efb2d159eb9c883e49.tar.bz2 | |
drm/i915: don't enable plane, pipe and PLL prematurely
On Ironlake+ we need to enable these in a specific order.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 98967f3..9dcad31 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4222,9 +4222,11 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, pipeconf &= ~PIPECONF_DOUBLE_WIDE; } - dspcntr |= DISPLAY_PLANE_ENABLE; - pipeconf |= PIPECONF_ENABLE; - dpll |= DPLL_VCO_ENABLE; + if (!HAS_PCH_SPLIT(dev)) { + dspcntr |= DISPLAY_PLANE_ENABLE; + pipeconf |= PIPECONF_ENABLE; + dpll |= DPLL_VCO_ENABLE; + } DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); drm_mode_debug_printmodeline(mode); |