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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-09-10 11:22:02 -0700
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-10 23:13:48 +0100
commitde9c27bf70964a8b257eaeb8f71f1898e9f4ac7d (patch)
treea9100da3d469397887eaa8b5f964e60df852bc6f
parent0e23b99d2599112a332136728e9250e688a08b0c (diff)
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drm/i915: don't write TU size to N1 reg
TU size is only part of the M1 and M2 regs, not the N regs. This keeps us from overwriting a reserved field. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 086df96..358c301 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4170,7 +4170,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
+ I915_WRITE(data_n1_reg, m_n.gmch_n);
I915_WRITE(link_m1_reg, m_n.link_m);
I915_WRITE(link_n1_reg, m_n.link_n);