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| author | Paul Mundt <lethal@linux-sh.org> | 2010-12-21 00:40:51 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-12-21 00:40:51 +0900 |
| commit | 8bcee1832d23869c2cdb6886ae5210b0143256f0 (patch) | |
| tree | 9fac190248ed9ed10fe4e6f7b1b4cda8eaef7ddd /arch/arm/mm/proc-macros.S | |
| parent | 5ce2a2ddb5d75d5e2371e58011fc21351bf278cb (diff) | |
| parent | 1cf215a5b43950d1a304373037828158057ff9fc (diff) | |
| download | kernel_samsung_aries-8bcee1832d23869c2cdb6886ae5210b0143256f0.zip kernel_samsung_aries-8bcee1832d23869c2cdb6886ae5210b0143256f0.tar.gz kernel_samsung_aries-8bcee1832d23869c2cdb6886ae5210b0143256f0.tar.bz2 | |
Merge branch 'rmobile/urgent' into rmobile-latest
Conflicts:
arch/arm/mach-shmobile/include/mach/entry-macro.S
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
| -rw-r--r-- | arch/arm/mm/proc-macros.S | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 7d63bea..b795afd 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -61,17 +61,27 @@ .endm /* - * cache_line_size - get the cache line size from the CSIDR register - * (available on ARMv7+). It assumes that the CSSR register was configured - * to access the L1 data cache CSIDR. + * dcache_line_size - get the minimum D-cache line size from the CTR register + * on ARMv7. */ .macro dcache_line_size, reg, tmp - mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR - and \tmp, \tmp, #7 @ cache line size encoding - mov \reg, #16 @ size offset + mrc p15, 0, \tmp, c0, c0, 1 @ read ctr + lsr \tmp, \tmp, #16 + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word mov \reg, \reg, lsl \tmp @ actual cache line size .endm +/* + * icache_line_size - get the minimum I-cache line size from the CTR register + * on ARMv7. + */ + .macro icache_line_size, reg, tmp + mrc p15, 0, \tmp, c0, c0, 1 @ read ctr + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word + mov \reg, \reg, lsl \tmp @ actual cache line size + .endm /* * Sanity check the PTE configuration for the code below - which makes |