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| author | Chirayu Desai <cdesai@cyanogenmod.org> | 2012-03-09 16:37:06 +0530 |
|---|---|---|
| committer | Chirayu Desai <chirayudesai1@gmail.com> | 2013-05-05 10:47:19 +0530 |
| commit | 939facfc7191b58c3d0fec275f93ed7d66a6c032 (patch) | |
| tree | 29a52eb6fa4cfe32b4471076cb1ed7d0643dbdd5 /arch/arm | |
| parent | f661100a75d28ad9ec0f3e9015794ffd69846f35 (diff) | |
| download | kernel_samsung_aries-939facfc7191b58c3d0fec275f93ed7d66a6c032.zip kernel_samsung_aries-939facfc7191b58c3d0fec275f93ed7d66a6c032.tar.gz kernel_samsung_aries-939facfc7191b58c3d0fec275f93ed7d66a6c032.tar.bz2 | |
add support for p1
Signed-off-by: Chirayu Desai <cdesai@cyanogenmod.org>
Signed-off-by: Humberto Borba <humberos@gmail.com>
Signed-off-by: Koudai Aono <koxudaxi@gmail.com>
Change-Id: I2dcbaee7f17852ed3ea4a5db2d103704027fe259
Diffstat (limited to 'arch/arm')
38 files changed, 11862 insertions, 622 deletions
diff --git a/arch/arm/configs/cyanogenmod_p1_defconfig b/arch/arm/configs/cyanogenmod_p1_defconfig new file mode 100644 index 0000000..8629e8c --- /dev/null +++ b/arch/arm/configs/cyanogenmod_p1_defconfig @@ -0,0 +1,446 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_KERNEL_LZMA=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="source/usr/p1_initramfs.list" +CONFIG_PANIC_TIMEOUT=5 +CONFIG_KALLSYMS_ALL=y +CONFIG_ASHMEM=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_PERF_COUNTERS=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_IOSCHED_ROW=y +CONFIG_DEFAULT_ROW=y +CONFIG_ARCH_S5PV210=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_S5P_HIGH_RES_TIMERS=y +CONFIG_S5PV210_SD_CH0_8BIT=y +CONFIG_MACH_P1=y +CONFIG_SAMSUNG_P1=y +CONFIG_SAMSUNG_P1C=n +CONFIG_SAMSUNG_P1LN=n +CONFIG_DVFS_LIMIT=y +CONFIG_S5PV210_SCLKFIMD_USE_VPLL=y +CONFIG_WIFI_CONTROL_FUNC=y +CONFIG_SEC_HEADSET=y +CONFIG_ARM_THUMBEE=y +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_COMPACTION=y +CONFIG_KSM=y +CONFIG_CMDLINE="console=ttyFIQ0,115200 init=/init" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_WAKELOCK=y +CONFIG_APM_EMULATION=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_TARGET_LOG=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_PHONET=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_WEXT is not set +CONFIG_CFG80211_ALLOW_RECONNECT=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_SAMSUNG=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_MISC_DEVICES=y +CONFIG_UID_STAT=y +CONFIG_APANIC=y +CONFIG_USB_SWITCH_FSA9480=y +CONFIG_30PIN_CONN=y +CONFIG_MHL_SII9234=y +CONFIG_SAMSUNG_MODEMCTL=y +CONFIG_MODEM_HAS_CRAPPY_BOOTLOADER=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_CRYPT=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_IFB=y +CONFIG_TUN=y +CONFIG_BCMDHD=y +CONFIG_BCMDHD_FW_PATH="/system/vendor/firmware/fw_bcmdhd.bin" +CONFIG_BCMDHD_NVRAM_PATH="/data/.nvram_net.txt" +CONFIG_DHD_USE_STATIC_BUF=y +CONFIG_PPP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_P1=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=y +CONFIG_TABLET_USB_AIPTEK=y +CONFIG_TABLET_USB_GTCO=y +CONFIG_TABLET_USB_HANWANG=y +CONFIG_TABLET_USB_KBTAB=y +CONFIG_TABLET_USB_WACOM=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_QT602240=y +CONFIG_TOUCHSCREEN_QT602240_ROT90=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +CONFIG_INPUT_BMA020=y +CONFIG_INPUT_AK8973B=y +CONFIG_INPUT_BH1721=y +CONFIG_INPUT_L3G4200D=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_S3C2410=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_BATTERY_MAX17042=y +CONFIG_CHARGER_SMB136=y +CONFIG_BATTERY_P1=y +CONFIG_MFD_MAX8998=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_MAX8998=y +CONFIG_VIBETONZ=m +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_ISX005=y +CONFIG_VIDEO_S5K6AAFX=y +CONFIG_VIDEO_S5K5CCGX=y +CONFIG_VIDEO_SAMSUNG=y +CONFIG_VIDEO_SAMSUNG_V4L2=y +CONFIG_VIDEO_FIMC=y +# CONFIG_VIDEO_FIMC_MIPI is not set +CONFIG_VIDEO_MFC50=y +CONFIG_VIDEO_JPEG_V2=y +CONFIG_HDMI_HPD=y +CONFIG_PVR_SGX=y +CONFIG_PVR_NEED_PVR_DPF=y +CONFIG_PVR_NEED_PVR_ASSERT=y +CONFIG_PVR_USSE_EDM_STATUS_DEBUG=y +CONFIG_PVR_LINUX_MEM_AREA_POOL=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_FB_S3C_NR_BUFFERS=7 +CONFIG_FB_S3C_LVDS=y +CONFIG_FB_S3C_MDNIE=y +CONFIG_FB_S3C_CMC623=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CMC623_PWM=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DEBUG=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_SAMSUNG_P1_WM8994=y +CONFIG_SND_WM8994_EXTENSIONS=y +CONFIG_UHID=y +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_PRODIKEYS=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +CONFIG_HID_ELECOM=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LOGITECH=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWII_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +CONFIG_HID_QUANTA=y +CONFIG_HID_ROCCAT_ARVO=y +CONFIG_HID_ROCCAT_KONE=y +CONFIG_HID_ROCCAT_KONEPLUS=y +CONFIG_HID_ROCCAT_KOVAPLUS=y +CONFIG_HID_ROCCAT_PYRA=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=y +CONFIG_HID_ZEROPLUS=y +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_G_ANDROID=y +CONFIG_USB_ANDROID_RNDIS_DWORD_ALIGNED=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ZRAM=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +CONFIG_FUSE_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_YAFFS_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_SYSV_FS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_USE_NEW_IDMAPPER=y +CONFIG_NFSD=y +CONFIG_CIFS=m +CONFIG_CIFS_STATS=y +CONFIG_CIFS_STATS2=y +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_ACL=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=m +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_SCHED_TRACER=y +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_S3C_UART=2 +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/cyanogenmod_p1ln_defconfig b/arch/arm/configs/cyanogenmod_p1ln_defconfig new file mode 100644 index 0000000..d546f45 --- /dev/null +++ b/arch/arm/configs/cyanogenmod_p1ln_defconfig @@ -0,0 +1,449 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_KERNEL_LZMA=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="source/usr/p1_initramfs.list" +CONFIG_PANIC_TIMEOUT=5 +CONFIG_KALLSYMS_ALL=y +CONFIG_ASHMEM=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_PERF_COUNTERS=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_IOSCHED_ROW=y +CONFIG_DEFAULT_ROW=y +CONFIG_ARCH_S5PV210=y +CONFIG_S3C_LOWLEVEL_UART_PORT=2 +CONFIG_S5P_HIGH_RES_TIMERS=y +CONFIG_S5PV210_SD_CH0_8BIT=y +CONFIG_MACH_P1=y +CONFIG_SAMSUNG_P1=n +CONFIG_SAMSUNG_P1C=n +CONFIG_SAMSUNG_P1LN=y +CONFIG_DVFS_LIMIT=y +CONFIG_S5PV210_SCLKFIMD_USE_VPLL=y +CONFIG_WIFI_CONTROL_FUNC=y +CONFIG_SEC_HEADSET=y +CONFIG_ARM_THUMBEE=y +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_COMPACTION=y +CONFIG_KSM=y +CONFIG_CMDLINE="console=ttyFIQ0,115200 init=/init" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_WAKELOCK=y +CONFIG_APM_EMULATION=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_TARGET_LOG=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_PHONET=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_WEXT is not set +CONFIG_CFG80211_ALLOW_RECONNECT=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_SAMSUNG=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_MISC_DEVICES=y +CONFIG_UID_STAT=y +CONFIG_APANIC=y +CONFIG_USB_SWITCH_FSA9480=y +CONFIG_30PIN_CONN=y +CONFIG_MHL_SII9234=y +CONFIG_SAMSUNG_MODEMCTL=y +CONFIG_MODEM_HAS_CRAPPY_BOOTLOADER=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_CRYPT=y +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_IFB=y +CONFIG_TUN=y +CONFIG_BCMDHD=y +CONFIG_BCMDHD_FW_PATH="/system/vendor/firmware/fw_bcmdhd.bin" +CONFIG_BCMDHD_NVRAM_PATH="/data/.nvram_net.txt" +CONFIG_DHD_USE_STATIC_BUF=y +CONFIG_PPP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_P1=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=y +CONFIG_TABLET_USB_AIPTEK=y +CONFIG_TABLET_USB_GTCO=y +CONFIG_TABLET_USB_HANWANG=y +CONFIG_TABLET_USB_KBTAB=y +CONFIG_TABLET_USB_WACOM=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_QT602240=y +CONFIG_TOUCHSCREEN_QT602240_ROT90=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +CONFIG_INPUT_BMA020=y +CONFIG_INPUT_AK8973B=y +CONFIG_INPUT_BH1721=y +CONFIG_INPUT_L3G4200D=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_S3C2410=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_BATTERY_MAX17042=y +CONFIG_CHARGER_SMB136=y +CONFIG_BATTERY_P1=y +CONFIG_MFD_MAX8998=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_MAX8998=y +CONFIG_VIBETONZ=m +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_ISX005=y +CONFIG_VIDEO_S5K6AAFX=y +CONFIG_VIDEO_S5K5CCGX=y +CONFIG_VIDEO_SAMSUNG=y +CONFIG_VIDEO_SAMSUNG_V4L2=y +# CONFIG_VIDEO_NM6XX is not set +CONFIG_VIDEO_FIMC=y +# CONFIG_VIDEO_FIMC_MIPI is not set +CONFIG_VIDEO_MFC50=y +CONFIG_VIDEO_JPEG_V2=y +CONFIG_HDMI_HPD=y +# CONFIG_VIDEO_TSI is not set +# CONFIG_ISDBT_NMI is not set +CONFIG_PVR_SGX=y +CONFIG_PVR_NEED_PVR_DPF=y +CONFIG_PVR_NEED_PVR_ASSERT=y +CONFIG_PVR_USSE_EDM_STATUS_DEBUG=y +CONFIG_PVR_LINUX_MEM_AREA_POOL=y +CONFIG_FB=y +CONFIG_FB_S3C=y +CONFIG_FB_S3C_NR_BUFFERS=7 +CONFIG_FB_S3C_LVDS=y +CONFIG_FB_S3C_MDNIE=y +CONFIG_FB_S3C_CMC623=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CMC623_PWM=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DEBUG=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_SAMSUNG=y +CONFIG_SND_SOC_SAMSUNG_P1_WM8994=y +CONFIG_SND_WM8994_EXTENSIONS=y +CONFIG_UHID=y +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_PRODIKEYS=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +CONFIG_HID_ELECOM=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LOGITECH=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWII_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +CONFIG_HID_QUANTA=y +CONFIG_HID_ROCCAT_ARVO=y +CONFIG_HID_ROCCAT_KONE=y +CONFIG_HID_ROCCAT_KONEPLUS=y +CONFIG_HID_ROCCAT_KOVAPLUS=y +CONFIG_HID_ROCCAT_PYRA=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=y +CONFIG_HID_ZEROPLUS=y +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_G_ANDROID=y +CONFIG_USB_ANDROID_RNDIS_DWORD_ALIGNED=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_SDHCI_S3C_DMA=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ZRAM=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +CONFIG_FUSE_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_YAFFS_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_SYSV_FS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_USE_NEW_IDMAPPER=y +CONFIG_NFSD=y +CONFIG_CIFS=m +CONFIG_CIFS_STATS=y +CONFIG_CIFS_STATS2=y +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_ACL=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=m +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_SCHED_TRACER=y +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_S3C_UART=2 +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRC_CCITT=y diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 298444a..efbebc5 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -45,7 +45,7 @@ unsigned long __stack_chk_guard __read_mostly; EXPORT_SYMBOL(__stack_chk_guard); #endif -#ifdef CONFIG_MACH_ARIES +#if defined(CONFIG_MACH_ARIES) || defined(CONFIG_MACH_P1) #include <mach/regs-clock.h> #endif @@ -149,7 +149,7 @@ void arm_machine_restart(char mode, const char *cmd) */ setup_mm_for_reboot(mode); -#ifdef CONFIG_MACH_ARIES +#if defined(CONFIG_MACH_ARIES) || defined(CONFIG_MACH_P1) writel(0x12345678, S5P_INFORM5); /* Turn off low power mode */ #endif diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 0ecf8ee..6ebf0fb 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -249,6 +249,28 @@ config MACH_ARIES help Machine support for Aries +config MACH_P1 + bool "P1" + select CPU_S5PV210 + select ARCH_DISCONTIGMEM_ENABLE + select S3C_DEV_WDT + select S3C_DEV_I2C1 + select S3C_DEV_I2C2 + select S5P_DEV_ONENAND + select HAVE_PWM + select SAMSUNG_DEV_PWM + select ARCH_HAS_CPUFREQ + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 if !S5PV210_SD_CH0_8BIT + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 if !S5PV210_SD_CH2_8BIT + select S5PV210_SETUP_SDHCI + select S5PV210_POWER_DOMAIN + select S5P_DEV_CSIS0 + select S5P_SETUP_MIPIPHY + help + Machine support for P1 + if MACH_ARIES choice prompt "Select phone Type" @@ -314,6 +336,53 @@ config SAMSUNG_EPIC endchoice endif +if MACH_P1 +choice +prompt "Select device type" +config PHONE_P1_GSM + bool "select p1 gsm" + depends on MACH_P1 + help + Select P1 GSM + +config PHONE_P1_CDMA + bool "select p1 cdma" + depends on MACH_P1 + help + Select P1 CDMA + +endchoice +endif + +if PHONE_P1_CDMA +choice +prompt "Select device model" +config SAMSUNG_P1C + bool "P1C" + depends on PHONE_P1_CDMA + help + Select Samsung Galaxy Tab CDMA SCH-I800/SPH-P100 + +endchoice +endif + +if PHONE_P1_GSM +choice +prompt "Select device model" +config SAMSUNG_P1 + bool "P1" + depends on PHONE_P1_GSM + help + Select Samsung Galaxy Tab GT-P1000 + +config SAMSUNG_P1LN + bool "P1L" + depends on PHONE_P1_GSM + help + Select Samsung Galaxy Tab GT-P1000L and GT-P1000N +endchoice +endif + config S5PV210_SETUP_FB bool depends on FB_S3C @@ -359,8 +428,43 @@ config CPU_DIDLE depends on CPU_IDLE default n +config S5PV210_SCLKFIMD_USE_VPLL + bool "Use VPLL for FIMD sclk source" + depends on FB_S3C + default n + help + Sclk fimd source use vpll, otherwise use mpll. + +choice + prompt "Target Pixel clock setting" + depends on FB_S3C + default TARGET_PCLK_54 + +config TARGET_PCLK_44_46 + bool "44.46Mhz" + help + Support 44.46Mhz + +config TARGET_PCLK_47_6 + bool "47.6Mhz" + help + Support 47.6Mhz + +config TARGET_PCLK_54 + bool "54Mhz" + help + Support 54Mhz + +endchoice + config WIFI_CONTROL_FUNC bool "Enable WiFi control function abstraction" help Enables Power/Reset/Carddetect function abstraction endif + +config SEC_HEADSET + tristate "SEC 2 Wire detection driver" + help + Provides support for detecting SEC 2 wire devices, such as wired + headset. diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index f146970..2dbd5b6 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -20,6 +20,11 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_S5PV210_POWER_DOMAIN) += power-domain.o obj-$(CONFIG_S5PV210_CORESIGHT) += coresight.o +# P1 compat +ifdef CONFIG_MACH_P1 +sec_switch-y := p1-sec_switch.o +endif + # machine support obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o @@ -47,6 +52,11 @@ obj-$(CONFIG_PHONE_ARIES_CDMA) += dev-s1-phone.o obj-$(CONFIG_PHONE_ARIES_CDMA) += level.o obj-$(CONFIG_PHONE_CRESPO) += dev-aries-phone.o +obj-$(CONFIG_MACH_P1) += mach-p1.o p1-rfkill.o sec_switch.o +obj-$(CONFIG_MACH_P1) += p1-watchdog.o +obj-$(CONFIG_PHONE_P1_GSM) += dev-p1-phone.o +obj-$(CONFIG_PHONE_P1) += level.o + # device support obj-y += dev-audio.o @@ -70,3 +80,5 @@ obj-$(CONFIG_S5PV210_SETUP_FIMC2) += setup-fimc2.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CPU_FREQ) += dev-cpufreq.o + +obj-$(CONFIG_SEC_HEADSET) += sec_jack.o diff --git a/arch/arm/mach-s5pv210/Makefile.boot b/arch/arm/mach-s5pv210/Makefile.boot index 667f731..4f09ccf 100644 --- a/arch/arm/mach-s5pv210/Makefile.boot +++ b/arch/arm/mach-s5pv210/Makefile.boot @@ -7,4 +7,8 @@ params_phys-$(CONFIG_MACH_HERRING) := 0x30000100 # override for Aries zreladdr-$(CONFIG_MACH_ARIES) := 0x30008000 -params_phys-$(CONFIG_MACH_ARIES) := 0x30000100
\ No newline at end of file +params_phys-$(CONFIG_MACH_ARIES) := 0x30000100 + +# override for P1 +zreladdr-$(CONFIG_MACH_P1) := 0x30008000 +params_phys-$(CONFIG_MACH_P1) := 0x30000100
\ No newline at end of file diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 6d3e609..dd7a6ff 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -458,7 +458,11 @@ static struct clk init_clocks_off[] = { }, { .name = "i2c", .id = 1, +#ifdef CONFIG_MACH_ARIES .parent = &clk_pclk_psys.clk, +#else + .parent = &clk_pclk_dsys.clk, +#endif .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 10), }, { @@ -521,6 +525,14 @@ static struct clk init_clocks_off[] = { .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 6), +#if defined (CONFIG_VIDEO_NM6XX) + }, { + .name = "i2s_v32", + .id = 2, + .parent = &clk_p, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 6), +#endif }, { .name = "spdif", .id = -1, @@ -550,7 +562,11 @@ static struct clk init_clocks_off[] = { #endif .name = "i2c-hdmiphy", .id = -1, +#ifdef CONFIG_MACH_ARIES .parent = &clk_pclk_psys.clk, +#else + .parent = &clk_pclk_dsys.clk, +#endif .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 11), }, { @@ -595,6 +611,15 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip4_ctrl, .ctrlbit = (1 << 3), }, +#if defined(CONFIG_VIDEO_TSI) + { + .name = "tsi", + .id = -1, + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = S5P_CLKGATE_IP2_TSI, + }, +#endif }; static struct clk init_dmaclocks[] = { @@ -1536,8 +1561,10 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) { pclkSrc = &clksrcs[ptr]; if (!strcmp(pclkSrc->clk.name, "sclk_mdnie")) { +#if !defined(CONFIG_FB_S3C_LVDS) clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); clk_set_rate(&pclkSrc->clk, 167*MHZ); +#endif } else if (!strcmp(pclkSrc->clk.name, "sclk_mmc")) { clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk); diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index cd40d7c..7be2fb7 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -131,10 +131,12 @@ static void s5pv210_idle(void) local_irq_enable(); } +#ifndef CONFIG_MACH_P1 static void s5pv210_sw_reset(void) { __raw_writel(0x1, S5P_SWRESET); } +#endif /* s5pv210_map_io * @@ -215,9 +217,10 @@ int __init s5pv210_init(void) /* set idle function */ pm_idle = s5pv210_idle; +#ifndef CONFIG_MACH_P1 /* set sw_reset function */ if (!(machine_is_herring() || machine_is_aries())) s5p_reset_hook = s5pv210_sw_reset; - +#endif return sysdev_register(&s5pv210_sysdev); } diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c index e712847..82ff777 100755..100644 --- a/arch/arm/mach-s5pv210/cpufreq.c +++ b/arch/arm/mach-s5pv210/cpufreq.c @@ -97,7 +97,7 @@ static unsigned int g_dvfs_high_lock_limit = 6; static unsigned int g_dvfslockval[DVFS_LOCK_TOKEN_NUM]; //static DEFINE_MUTEX(dvfs_high_lock); #endif - +#ifdef CONFIG_MACH_ARIES const unsigned long arm_volt_max = 1350000; const unsigned long int_volt_max = 1250000; @@ -127,7 +127,37 @@ static struct s5pv210_dvs_conf dvs_conf[] = { .int_volt = 1000000, }, }; +#else // CONFIG_MACH_P1 +const unsigned long arm_volt_max = 1450000; +const unsigned long int_volt_max = 1250000; +static struct s5pv210_dvs_conf dvs_conf[] = { + [OC0] = { + .arm_volt = 1450000, + .int_volt = 1200000, + }, + [L0] = { + .arm_volt = 1350000, + .int_volt = 1100000, + }, + [L1] = { + .arm_volt = 1275000, + .int_volt = 1100000, + }, + [L2] = { + .arm_volt = 1050000, + .int_volt = 1100000, + }, + [L3] = { + .arm_volt = 950000, + .int_volt = 1100000, + }, + [L4] = { + .arm_volt = 950000, + .int_volt = 1000000, + }, +}; +#endif static u32 clkdiv_val[6][11] = { /* * Clock divider value for following @@ -640,7 +670,11 @@ static int __init s5pv210_cpu_init(struct cpufreq_policy *policy) cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu); +#if CONFIG_MACH_ARIES policy->cpuinfo.transition_latency = 40000; +#else // CONFIG_MACH_P1 + policy->cpuinfo.transition_latency = 100000; /* 1us */ +#endif #ifdef CONFIG_DVFS_LIMIT int i; diff --git a/arch/arm/mach-s5pv210/dev-fiqdbg.c b/arch/arm/mach-s5pv210/dev-fiqdbg.c index 16ef49b..c2ddf81 100644 --- a/arch/arm/mach-s5pv210/dev-fiqdbg.c +++ b/arch/arm/mach-s5pv210/dev-fiqdbg.c @@ -25,6 +25,32 @@ #include <mach/map.h> #include <plat/regs-serial.h> +#ifdef CONFIG_KEYBOARD_P1 +static void *g_base; +extern bool keyboard_enable; +extern void send_keyevent(unsigned int key_code); +void dock_keyboard_tx(u8 val) +{ + writel(val, g_base + S3C2410_UTXH); +} +EXPORT_SYMBOL(dock_keyboard_tx); + +int change_console_baud_rate(int baud) +{ + if(baud == 9600) + { + writel(431, g_base + S3C2410_UBRDIV); + } + else + { + writel(35, g_base + S3C2410_UBRDIV); + } + return 0; + +} +EXPORT_SYMBOL(change_console_baud_rate); +#endif + static void *s5pv210_fiqdbg_get_base(struct platform_device *pdev) { return S5P_VA_UART0 + S3C_UART_OFFSET * pdev->id; @@ -54,6 +80,7 @@ static int s5pv210_fiqdbg_uart_getc(struct platform_device *pdev) { void *base = s5pv210_fiqdbg_get_base(pdev); unsigned int ufstat; + u8 rx_ch; if (readl(base + S3C2410_UERSTAT) & S3C2410_UERSTAT_BREAK) return FIQ_DEBUGGER_BREAK; @@ -61,7 +88,15 @@ static int s5pv210_fiqdbg_uart_getc(struct platform_device *pdev) ufstat = readl(base + S3C2410_UFSTAT); if (!(ufstat & (S5PV210_UFSTAT_RXMASK | S5PV210_UFSTAT_RXFULL))) return FIQ_DEBUGGER_NO_CHAR; - return readb(base + S3C2410_URXH); + + rx_ch = readb(base + S3C2410_URXH); + +#ifdef CONFIG_KEYBOARD_P1 + if(keyboard_enable) + send_keyevent(rx_ch); +#endif + + return rx_ch; } static void s5pv210_fiqdbg_uart_putc(struct platform_device *pdev, @@ -117,7 +152,9 @@ static int s5pv210_fiqdbg_uart_init(struct platform_device *pdev) writel(0x808, base + S3C2443_DIVSLOT); writel(0xc, base + S5P_UINTM); writel(0xf, base + S5P_UINTP); - +#ifdef CONFIG_KEYBOARD_P1 + g_base = base; +#endif return 0; } diff --git a/arch/arm/mach-s5pv210/dev-p1-phone.c b/arch/arm/mach-s5pv210/dev-p1-phone.c new file mode 100644 index 0000000..393f2b5 --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-p1-phone.c @@ -0,0 +1,147 @@ +/* linux/arch/arm/mach-s5pv210/dev-p1-phone.c + * Copyright (C) 2010 Samsung Electronics. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/gpio-p1.h> + +#include "../../../drivers/misc/samsung_modemctl/onedram/onedram.h" +#include "../../../drivers/misc/samsung_modemctl/modemctl/modemctl.h" + +/* onedram */ +static void onedram_cfg_gpio(void) +{ + s3c_gpio_cfgpin(GPIO_nINT_ONEDRAM_AP, S3C_GPIO_SFN(GPIO_nINT_ONEDRAM_AP_AF)); + s3c_gpio_setpull(GPIO_nINT_ONEDRAM_AP, S3C_GPIO_PULL_UP); + irq_set_irq_type(GPIO_nINT_ONEDRAM_AP, IRQ_TYPE_LEVEL_LOW); +} + +static struct onedram_platform_data onedram_data = { + .cfg_gpio = onedram_cfg_gpio, + }; + +static struct resource onedram_res[] = { + [0] = { + .start = (S5PV210_PA_SDRAM + 0x05000000), + .end = (S5PV210_PA_SDRAM + 0x05000000 + SZ_16M - 1), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_EINT11, + .end = IRQ_EINT11, + .flags = IORESOURCE_IRQ, + }, + }; + +static struct platform_device onedram = { + .name = "onedram", + .id = -1, + .num_resources = ARRAY_SIZE(onedram_res), + .resource = onedram_res, + .dev = { + .platform_data = &onedram_data, + }, + }; + +/* Modem control */ + +static void modemctl_cfg_gpio(void); + +static struct modemctl_platform_data mdmctl_data = { + .name = "xmm", + .gpio_phone_on = NULL, + .gpio_phone_active = GPIO_PHONE_ACTIVE, + .gpio_pda_active = GPIO_PDA_ACTIVE, + .gpio_cp_reset = GPIO_CP_RST, + .gpio_reset_req_n = GPIO_RESET_REQ_N, + .gpio_sim_ndetect = GPIO_SIM_nDETECT, + .cfg_gpio = modemctl_cfg_gpio, + }; + +static struct resource mdmctl_res[] = { + [0] = { + .start = IRQ_EINT15, + .end = IRQ_EINT15, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = IRQ_EINT(27), + .end = IRQ_EINT(27), + .flags = IORESOURCE_IRQ, + }, + }; + +static struct platform_device modemctl = { + .name = "modemctl", + .id = -1, + .num_resources = ARRAY_SIZE(mdmctl_res), + .resource = mdmctl_res, + .dev = { + .platform_data = &mdmctl_data, + }, + }; + +static void modemctl_cfg_gpio(void) +{ + int err = 0; + + unsigned gpio_phone_on = mdmctl_data.gpio_phone_on; + unsigned gpio_phone_active = mdmctl_data.gpio_phone_active; + unsigned gpio_cp_rst = mdmctl_data.gpio_cp_reset; + unsigned gpio_pda_active = mdmctl_data.gpio_pda_active; + unsigned gpio_sim_ndetect = mdmctl_data.gpio_sim_ndetect; + + err = gpio_request(gpio_cp_rst, "CP_RST"); + if (err) { + printk("fail to request gpio %s\n","CP_RST"); + } else { + gpio_direction_output(gpio_cp_rst, GPIO_LEVEL_LOW); + s3c_gpio_setpull(gpio_cp_rst, S3C_GPIO_PULL_NONE); + } + err = gpio_request(gpio_pda_active, "PDA_ACTIVE"); + if (err) { + printk("fail to request gpio %s\n","PDA_ACTIVE"); + } else { + gpio_direction_output(gpio_pda_active, GPIO_LEVEL_LOW); + s3c_gpio_setpull(gpio_pda_active, S3C_GPIO_PULL_NONE); + } + + if (mdmctl_data.gpio_reset_req_n) { + err = gpio_request(mdmctl_data.gpio_reset_req_n, "RST_REQN"); + if (err) { + printk("fail to request gpio %s\n","RST_REQN"); + } else + gpio_direction_output(mdmctl_data.gpio_reset_req_n, GPIO_LEVEL_LOW); + } + + s3c_gpio_cfgpin(gpio_phone_active, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_phone_active, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_phone_active, IRQ_TYPE_EDGE_BOTH); + + s3c_gpio_cfgpin(gpio_sim_ndetect, S3C_GPIO_SFN(0xF)); + s3c_gpio_setpull(gpio_sim_ndetect, S3C_GPIO_PULL_NONE); + irq_set_irq_type(gpio_sim_ndetect, IRQ_TYPE_EDGE_BOTH); +} + +static int __init p1_init_phone_interface(void) +{ + platform_device_register(&modemctl); + platform_device_register(&onedram); + return 0; +} +device_initcall(p1_init_phone_interface); diff --git a/arch/arm/mach-s5pv210/include/mach/gpio-p1.h b/arch/arm/mach-s5pv210/include/mach/gpio-p1.h index f36cfc7..0b969dc 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio-p1.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio-p1.h @@ -1,7 +1,7 @@ /* linux/arch/arm/mach-s5pv210/include/mach/gpio-p1.h * * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ + * http://www.samsung.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -10,624 +10,716 @@ #ifndef __GPIO_P1_H_ #define __GPIO_P1_H_ -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 -#define GPIO_LEVEL_NONE 2 -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#define GPIO_LEVEL_NONE 2 +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +//GPA0 +//------------------------------------------------------------- +#define GPIO_BT_UART_RXD S5PV210_GPA0(0) +#define GPIO_BT_UART_RXD_AF 2 +#define GPIO_BT_RXD S5PV210_GPA0(0) +#define GPIO_BT_RXD_AF 2 +#define GPIO_BT_UART_TXD S5PV210_GPA0(1) +#define GPIO_BT_UART_TXD_AF 2 +#define GPIO_BT_TXD S5PV210_GPA0(1) +#define GPIO_BT_TXD_AF 2 +#define GPIO_BT_UART_CTS S5PV210_GPA0(2) +#define GPIO_BT_UART_CTS_AF 2 +#define GPIO_BT_CTS S5PV210_GPA0(2) +#define GPIO_BT_CTS_AF 2 +#define GPIO_BT_UART_RTS S5PV210_GPA0(3) +#define GPIO_BT_UART_RTS_AF 2 +#define GPIO_BT_RTS S5PV210_GPA0(3) +#define GPIO_BT_RTS_AF 2 +#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) +#define GPIO_GPS_UART_RXD_AF 2 +#define GPIO_GPS_RXD S5PV210_GPA0(4) +#define GPIO_GPS_RXD_AF 2 +#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) +#define GPIO_GPS_UART_TXD_AF 2 +#define GPIO_GPS_TXD S5PV210_GPA0(5) +#define GPIO_GPS_TXD_AF 2 +#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) +#define GPIO_GPS_UART_CTS_AF 2 +#define GPIO_GPS_CTS S5PV210_GPA0(6) +#define GPIO_GPS_CTS_AF 2 +#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) +#define GPIO_GPS_UART_RTS_AF 2 +#define GPIO_GPS_RTS S5PV210_GPA0(7) +#define GPIO_GPS_RTS_AF 2 + +//GPA1 +//------------------------------------------------------------- +#define GPIO_AP_RXD S5PV210_GPA1(0) +#define GPIO_AP_RXD_AF 2 +#define GPIO_AP_TXD S5PV210_GPA1(1) +#define GPIO_AP_TXD_AF 2 +#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) +#define GPIO_AP_FLM_RXD_AF 2 +#define GPIO_FLM_RXD S5PV210_GPA1(2) +#define GPIO_FLM_RXD_AF 2 +#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) +#define GPIO_AP_FLM_TXD_AF 2 +#define GPIO_FLM_TXD S5PV210_GPA1(3) +#define GPIO_FLM_TXD_AF 2 + +//GPB** +//------------------------------------------------------------- +#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) +#define GPIO_MSENSE_nRST S5PV210_GPB(1) +#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) +#define GPIO_BT_nRST S5PV210_GPB(3) + +#if defined(CONFIG_SAMSUNG_P1LN) + +#define GPIO_HWREV_MODE3 S5PV210_GPB(4) +#define GPIO_HWREV_MODE2 S5PV210_GPB(5) +#define GPIO_HWREV_MODE1 S5PV210_GPB(6) +#define GPIO_HWREV_MODE0 S5PV210_GPB(7) + +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) + +#define GPIO_BOOT_MODE S5PV210_GPB(4) +//#define GPIO_WLAN_BT_EN S5PV210_GPB(5) +#define GPIO_GPB6 S5PV210_GPB(6) +#define GPIO_GPB7 S5PV210_GPB(7) -#define GPIO_BT_UART_RXD S5PV210_GPA0(0) -#define GPIO_BT_UART_RXD_AF 2 - -#define GPIO_BT_UART_TXD S5PV210_GPA0(1) -#define GPIO_BT_UART_TXD_AF 2 - -#define GPIO_BT_UART_CTS S5PV210_GPA0(2) -#define GPIO_BT_UART_CTS_AF 2 - -#define GPIO_BT_UART_RTS S5PV210_GPA0(3) -#define GPIO_BT_UART_RTS_AF 2 - -#define GPIO_GPS_UART_RXD S5PV210_GPA0(4) -#define GPIO_GPS_UART_RXD_AF 2 - -#define GPIO_GPS_UART_TXD S5PV210_GPA0(5) -#define GPIO_GPS_UART_TXD_AF 2 - -#define GPIO_GPS_UART_CTS S5PV210_GPA0(6) -#define GPIO_GPS_UART_CTS_AF 2 - -#define GPIO_GPS_UART_RTS S5PV210_GPA0(7) -#define GPIO_GPS_UART_RTS_AF 2 - -#define GPIO_AP_RXD S5PV210_GPA1(0) -#define GPIO_AP_RXD_AF 2 - -#define GPIO_AP_TXD S5PV210_GPA1(1) -#define GPIO_AP_TXD_AF 2 - -#define GPIO_AP_FLM_RXD S5PV210_GPA1(2) -#define GPIO_AP_FLM_RXD_AF 2 - -#define GPIO_AP_FLM_TXD S5PV210_GPA1(3) -#define GPIO_AP_FLM_TXD_AF 2 - -#define GPIO_CAM_VGA_nSTBY S5PV210_GPB(0) - -#define GPIO_MSENSE_nRST S5PV210_GPB(1) - -#define GPIO_CAM_VGA_nRST S5PV210_GPB(2) - -#define GPIO_BT_nRST S5PV210_GPB(3) - -#define GPIO_BOOT_MODE S5PV210_GPB(4) - -#define GPIO_WLAN_BT_EN S5PV210_GPB(5) - -#define GPIO_GPB6 S5PV210_GPB(6) +#endif -#define GPIO_GPB7 S5PV210_GPB(7) +#define GPIO_TOUCH_RST S5PV210_GPB(6) +#define GPIO_TOUCH_ST_AF 1 -#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) -#define GPIO_REC_PCM_CLK_AF 3 -#define GPIO_GPC01 S5PV210_GPC0(1) +//GPC0 +//------------------------------------------------------------- +#define GPIO_REC_PCM_CLK S5PV210_GPC0(0) +#define GPIO_REC_PCM_CLK_AF 3 +#define GPIO_GPC01 S5PV210_GPC0(1) +#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) +#define GPIO_REC_PCM_SYNC_AF 3 +#define GPIO_REC_PCM_IN S5PV210_GPC0(3) +#define GPIO_REC_PCM_IN_AF 3 +#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) +#define GPIO_REC_PCM_OUT_AF 3 -#define GPIO_REC_PCM_SYNC S5PV210_GPC0(2) -#define GPIO_REC_PCM_SYNC_AF 3 +//GPC1** +//------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_REC_PCM_IN S5PV210_GPC0(3) -#define GPIO_REC_PCM_IN_AF 3 +#define GPIO_I2S_SCLK_18V S5PV210_GPC1(0) +#define GPIO_I2S_MCLK_18V S5PV210_GPC1(1) +#define GPIO_I2S_LRCLK_18V S5PV210_GPC1(2) +#define GPIO_I2S_DATA_18V S5PV210_GPC1(3) +#define GPIO_GPC14 S5PV210_GPC1(4) -#define GPIO_REC_PCM_OUT S5PV210_GPC0(4) -#define GPIO_REC_PCM_OUT_AF 3 +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) #define BLOW_PCM_CLK S5PV210_GPC1(0) - -#define GPIO_GPC11 S5PV210_GPC1(1) - -#define GPIO_GPC12 S5PV210_GPC1(2) - -#define GPIO_GPC13 S5PV210_GPC1(3) - -#define GPIO_GPC14 S5PV210_GPC1(4) - +#define GPIO_GPC11 S5PV210_GPC1(1) +#define GPIO_GPC12 S5PV210_GPC1(2) +#define GPIO_GPC13 S5PV210_GPC1(3) +#define GPIO_GPC14 S5PV210_GPC1(4) // CMC623 -#define GPIO_CMC_SLEEP S5PV210_GPC1(0) -#define GPIO_CMC_SLEEP_AF 2 +#define GPIO_CMC_SLEEP S5PV210_GPC1(0) +#define GPIO_CMC_SLEEP_AF 2 #define GPIO_CMC_EN S5PV210_GPC1(1) #define GPIO_CMC_EN_AF 2 -#define GPIO_CMC_RST S5PV210_GPC1(2) +#define GPIO_CMC_RST S5PV210_GPC1(2) #define GPIO_CMC_RST_AF 2 -#define GPIO_CMC_SHDN S5PV210_GPC1(3) -#define GPIO_CMC_SHDN_AF 2 +#define GPIO_CMC_SHDN S5PV210_GPC1(3) +#define GPIO_CMC_SHDN_AF 2 #define GPIO_CMC_BYPASS S5PV210_GPC1(4) #define GPIO_CMC_BYPASS_AF 2 -#define GPIO_GPD00 S5PV210_GPD0(0) - -#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) - -#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) - -#define GPIO_GPD03 S5PV210_GPD0(3) - -#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) -#define GPIO_CAM_SDA_29V_AF 2 - -#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) -#define GPIO_CAM_SCL_29V_AF 2 - -#define GYRO_SDA_28V S5PV210_GPD1(2) -#define GYRO_SCL_28V S5PV210_GPD1(3) - -#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) -#define GPIO_TSP_SDA_28V_AF 2 - -#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) -#define GPIO_TSP_SCL_28V_AF 2 -#define GPIO_CAM_PCLK S5PV210_GPE0(0) -#define GPIO_CAM_PCLK_AF 2 - -#define GPIO_CAM_VSYNC S5PV210_GPE0(1) -#define GPIO_CAM_VSYNC_AF 2 - -#define GPIO_CAM_HSYNC S5PV210_GPE0(2) -#define GPIO_CAM_HSYNC_AF 2 - -#define GPIO_CAM_D0 S5PV210_GPE0(3) -#define GPIO_CAM_D0_AF 2 - -#define GPIO_CAM_D1 S5PV210_GPE0(4) -#define GPIO_CAM_D1_AF 2 - -#define GPIO_CAM_D2 S5PV210_GPE0(5) -#define GPIO_CAM_D2_AF 2 - -#define GPIO_CAM_D3 S5PV210_GPE0(6) -#define GPIO_CAM_D3_AF 2 - -#define GPIO_CAM_D4 S5PV210_GPE0(7) -#define GPIO_CAM_D4_AF 2 - -#define GPIO_CAM_D5 S5PV210_GPE1(0) -#define GPIO_CAM_D5_AF 2 - -#define GPIO_CAM_D6 S5PV210_GPE1(1) -#define GPIO_CAM_D6_AF 2 - -#define GPIO_CAM_D7 S5PV210_GPE1(2) -#define GPIO_CAM_D7_AF 2 - -#define GPIO_CAM_MCLK S5PV210_GPE1(3) -#define GPIO_CAM_MCLK_AF 2 - -#define GPIO_GPE14 S5PV210_GPE1(4) - -#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) -#define GPIO_DISPLAY_HSYNC_AF 2 - -#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) -#define GPIO_DISPLAY_VSYNC_AF 2 - -#define GPIO_DISPLAY_DE S5PV210_GPF0(2) -#define GPIO_DISPLAY_DE_AF 2 - -#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) -#define GPIO_DISPLAY_PCLK_AF 2 - -#define GPIO_LCD_D0 S5PV210_GPF0(4) -#define GPIO_LCD_D0_AF 2 - -#define GPIO_LCD_D1 S5PV210_GPF0(5) -#define GPIO_LCD_D1_AF 2 - -#define GPIO_LCD_D2 S5PV210_GPF0(6) -#define GPIO_LCD_D2_AF 2 - -#define GPIO_LCD_D3 S5PV210_GPF0(7) -#define GPIO_LCD_D3_AF 2 - -#define GPIO_LCD_D4 S5PV210_GPF1(0) -#define GPIO_LCD_D4_AF 2 - -#define GPIO_LCD_D5 S5PV210_GPF1(1) -#define GPIO_LCD_D5_AF 2 - -#define GPIO_LCD_D6 S5PV210_GPF1(2) -#define GPIO_LCD_D6_AF 2 - -#define GPIO_LCD_D7 S5PV210_GPF1(3) -#define GPIO_LCD_D7_AF 2 - -#define GPIO_LCD_D8 S5PV210_GPF1(4) -#define GPIO_LCD_D8_AF 2 - -#define GPIO_LCD_D9 S5PV210_GPF1(5) -#define GPIO_LCD_D9_AF 2 - -#define GPIO_LCD_D10 S5PV210_GPF1(6) -#define GPIO_LCD_D10_AF 2 - -#define GPIO_LCD_D11 S5PV210_GPF1(7) -#define GPIO_LCD_D11_AF 2 - -#define GPIO_LCD_D12 S5PV210_GPF2(0) -#define GPIO_LCD_D12_AF 2 - -#define GPIO_LCD_D13 S5PV210_GPF2(1) -#define GPIO_LCD_D13_AF 2 - -#define GPIO_LCD_D14 S5PV210_GPF2(2) -#define GPIO_LCD_D14_AF 2 - -#define GPIO_LCD_D15 S5PV210_GPF2(3) -#define GPIO_LCD_D15_AF 2 - -#define GPIO_LCD_D16 S5PV210_GPF2(4) -#define GPIO_LCD_D16_AF 2 +#endif -#define GPIO_LCD_D17 S5PV210_GPF2(5) -#define GPIO_LCD_D17_AF 2 +//GPD0** +//------------------------------------------------------------- +#define GPIO_GPD00 S5PV210_GPD0(0) -#define GPIO_LCD_D18 S5PV210_GPF2(6) -#define GPIO_LCD_D18_AF 2 +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_LCD_D19 S5PV210_GPF2(7) -#define GPIO_LCD_D19_AF 2 +#define GPIO_ATV_RSTn_REV07 S5PV210_GPD0(1) +#define GPIO_HWREV_MODE4 S5PV210_GPD0(2) -#define GPIO_LCD_D20 S5PV210_GPF3(0) -#define GPIO_LCD_D20_AF 2 +#endif -#define GPIO_LCD_D21 S5PV210_GPF3(1) -#define GPIO_LCD_D21_AF 2 +#define GPIO_VIBTONE_PWM S5PV210_GPD0(1) +#define GPIO_VIBTONE_PWM1 S5PV210_GPD0(2) -#define GPIO_LCD_D22 S5PV210_GPF3(2) -#define GPIO_LCD_D22_AF 2 +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_LCD_D23 S5PV210_GPF3(3) -#define GPIO_LCD_D23_AF 2 +#define GPIO_ATV_RSTn_REV10 S5PV210_GPD0(3) -#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) -#define GPIO_GPF35 S5PV210_GPF3(5) +#define GPIO_GPD03 S5PV210_GPD0(3) -#define GPIO_NAND_CLK S5PV210_GPG0(0) -#define GPIO_NAND_CLK_AF 2 +#endif -#define GPIO_NAND_CMD S5PV210_GPG0(1) -#define GPIO_NAND_CMD_AF 2 +//GPD1 +//------------------------------------------------------------- +#define GPIO_CAM_SDA_29V S5PV210_GPD1(0) +#define GPIO_CAM_SDA_29V_AF 2 +#define GPIO_CAM_SCL_29V S5PV210_GPD1(1) +#define GPIO_CAM_SCL_29V_AF 2 +#define GYRO_SDA_28V S5PV210_GPD1(2) +#define GYRO_SCL_28V S5PV210_GPD1(3) +#define GPIO_TSP_SDA_28V S5PV210_GPD1(4) +#define GPIO_TSP_SDA_28V_AF 2 +#define GPIO_TSP_SCL_28V S5PV210_GPD1(5) +#define GPIO_TSP_SCL_28V_AF 2 + +//GPE0 +//------------------------------------------------------------- +#define GPIO_CAM_PCLK S5PV210_GPE0(0) +#define GPIO_CAM_PCLK_AF 2 +#define GPIO_CAM_VSYNC S5PV210_GPE0(1) +#define GPIO_CAM_VSYNC_AF 2 +#define GPIO_CAM_HSYNC S5PV210_GPE0(2) +#define GPIO_CAM_HSYNC_AF 2 +#define GPIO_CAM_D0 S5PV210_GPE0(3) +#define GPIO_CAM_D0_AF 2 +#define GPIO_CAM_D1 S5PV210_GPE0(4) +#define GPIO_CAM_D1_AF 2 +#define GPIO_CAM_D2 S5PV210_GPE0(5) +#define GPIO_CAM_D2_AF 2 +#define GPIO_CAM_D3 S5PV210_GPE0(6) +#define GPIO_CAM_D3_AF 2 +#define GPIO_CAM_D4 S5PV210_GPE0(7) +#define GPIO_CAM_D4_AF 2 + +//GPE1 +//------------------------------------------------------------- +#define GPIO_CAM_D5 S5PV210_GPE1(0) +#define GPIO_CAM_D5_AF 2 +#define GPIO_CAM_D6 S5PV210_GPE1(1) +#define GPIO_CAM_D6_AF 2 +#define GPIO_CAM_D7 S5PV210_GPE1(2) +#define GPIO_CAM_D7_AF 2 +#define GPIO_CAM_MCLK S5PV210_GPE1(3) +#define GPIO_CAM_MCLK_AF 2 +#define GPIO_GPE14 S5PV210_GPE1(4) + +//GPF0 +//------------------------------------------------------------- +#define GPIO_DISPLAY_HSYNC S5PV210_GPF0(0) +#define GPIO_DISPLAY_HSYNC_AF S3C_GPIO_SFN(2) +#define GPIO_DISPLAY_VSYNC S5PV210_GPF0(1) +#define GPIO_DISPLAY_VSYNC_AF S3C_GPIO_SFN(2) +#define GPIO_DISPLAY_DE S5PV210_GPF0(2) +#define GPIO_DISPLAY_DE_AF S3C_GPIO_SFN(2) +#define GPIO_DISPLAY_PCLK S5PV210_GPF0(3) +#define GPIO_DISPLAY_PCLK_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D0 S5PV210_GPF0(4) +#define GPIO_LCD_D0_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D1 S5PV210_GPF0(5) +#define GPIO_LCD_D1_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D2 S5PV210_GPF0(6) +#define GPIO_LCD_D2_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D3 S5PV210_GPF0(7) +#define GPIO_LCD_D3_AF S3C_GPIO_SFN(2) + +//GPF1 +//------------------------------------------------------------- +#define GPIO_LCD_D4 S5PV210_GPF1(0) +#define GPIO_LCD_D4_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D5 S5PV210_GPF1(1) +#define GPIO_LCD_D5_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D6 S5PV210_GPF1(2) +#define GPIO_LCD_D6_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D7 S5PV210_GPF1(3) +#define GPIO_LCD_D7_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D8 S5PV210_GPF1(4) +#define GPIO_LCD_D8_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D9 S5PV210_GPF1(5) +#define GPIO_LCD_D9_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D10 S5PV210_GPF1(6) +#define GPIO_LCD_D10_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D11 S5PV210_GPF1(7) +#define GPIO_LCD_D11_AF S3C_GPIO_SFN(2) + +//GPF2 +//------------------------------------------------------------- +#define GPIO_LCD_D12 S5PV210_GPF2(0) +#define GPIO_LCD_D12_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D13 S5PV210_GPF2(1) +#define GPIO_LCD_D13_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D14 S5PV210_GPF2(2) +#define GPIO_LCD_D14_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D15 S5PV210_GPF2(3) +#define GPIO_LCD_D15_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D16 S5PV210_GPF2(4) +#define GPIO_LCD_D16_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D17 S5PV210_GPF2(5) +#define GPIO_LCD_D17_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D18 S5PV210_GPF2(6) +#define GPIO_LCD_D18_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D19 S5PV210_GPF2(7) +#define GPIO_LCD_D19_AF S3C_GPIO_SFN(2) + +//GPF3 +//------------------------------------------------------------- +#define GPIO_LCD_D20 S5PV210_GPF3(0) +#define GPIO_LCD_D20_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D21 S5PV210_GPF3(1) +#define GPIO_LCD_D21_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D22 S5PV210_GPF3(2) +#define GPIO_LCD_D22_AF S3C_GPIO_SFN(2) +#define GPIO_LCD_D23 S5PV210_GPF3(3) +#define GPIO_LCD_D23_AF S3C_GPIO_SFN(2) +#define GPIO_CODEC_LDO_EN S5PV210_GPF3(4) +#define GPIO_GPF35 S5PV210_GPF3(5) + +//GPG0** +//------------------------------------------------------------- +#define GPIO_NAND_CLK S5PV210_GPG0(0) +#define GPIO_NAND_CLK_AF 2 +#define GPIO_NAND_CMD S5PV210_GPG0(1) +#define GPIO_NAND_CMD_AF 2 + +#if defined(CONFIG_SAMSUNG_P1LN) + +#define GPIO_TOUCH_INT S5PV210_GPG0(2) + +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) #define GPIO_ALS_SCL_28V S5PV210_GPG0(2) -#define GPIO_NAND_D0 S5PV210_GPG0(3) -#define GPIO_NAND_D0_AF 2 +#endif -#define GPIO_NAND_D1 S5PV210_GPG0(4) -#define GPIO_NAND_D1_AF 2 +#define GPIO_NAND_D0 S5PV210_GPG0(3) +#define GPIO_NAND_D0_AF 2 +#define GPIO_NAND_D1 S5PV210_GPG0(4) +#define GPIO_NAND_D1_AF 2 +#define GPIO_NAND_D2 S5PV210_GPG0(5) +#define GPIO_NAND_D2_AF 2 +#define GPIO_NAND_D3 S5PV210_GPG0(6) +#define GPIO_NAND_D3_AF 2 -#define GPIO_NAND_D2 S5PV210_GPG0(5) -#define GPIO_NAND_D2_AF 2 +//GPG1** +//------------------------------------------------------------- +#define GPIO_GPS_nRST S5PV210_GPG1(0) +#define GPIO_GPS_PWR_EN S5PV210_GPG1(1) -#define GPIO_NAND_D3 S5PV210_GPG0(6) -#define GPIO_NAND_D3_AF 2 +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_GPS_nRST S5PV210_GPG1(0) +#define GPIO_ISDBT_RSTn S5PV210_GPG1(2) -#define GPIO_GPS_PWR_EN S5PV210_GPG1(1) +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) #define GPIO_WLAN_RST S5PV210_GPG1(2) -#define GPIO_NAND_D4 S5PV210_GPG1(3) -#define GPIO_NAND_D4_AF 3 - -#define GPIO_NAND_D5 S5PV210_GPG1(4) -#define GPIO_NAND_D5_AF 3 - -#define GPIO_NAND_D6 S5PV210_GPG1(5) -#define GPIO_NAND_D6_AF 3 - -#define GPIO_NAND_D7 S5PV210_GPG1(6) -#define GPIO_NAND_D7_AF 3 - -#define GPIO_T_FLASH_CLK S5PV210_GPG2(0) -#define GPIO_T_FLASH_CLK_AF 2 - -#define GPIO_T_FLASH_CMD S5PV210_GPG2(1) -#define GPIO_T_FLASH_CMD_AF 2 - -#define GPIO_ALS_SDA_28V S5PV210_GPG2(2) - -#define GPIO_T_FLASH_D0 S5PV210_GPG2(3) -#define GPIO_T_FLASH_D0_AF 2 - -#define GPIO_T_FLASH_D1 S5PV210_GPG2(4) -#define GPIO_T_FLASH_D1_AF 2 - -#define GPIO_T_FLASH_D2 S5PV210_GPG2(5) -#define GPIO_T_FLASH_D2_AF 2 - -#define GPIO_T_FLASH_D3 S5PV210_GPG2(6) -#define GPIO_T_FLASH_D3_AF 2 - -#define GPIO_WLAN_SDIO_CLK S5PV210_GPG3(0) -#define GPIO_WLAN_SDIO_CLK_AF 2 - -#define GPIO_WLAN_SDIO_CMD S5PV210_GPG3(1) -#define GPIO_WLAN_SDIO_CMD_AF 2 - -#define GPIO_WLAN_nRST S5PV210_GPG3(2) -#define GPIO_WLAN_nRST_AF 1 - -#define GPIO_WLAN_SDIO_D0 S5PV210_GPG3(3) -#define GPIO_WLAN_SDIO_D0_AF 2 - -#define GPIO_WLAN_SDIO_D1 S5PV210_GPG3(4) -#define GPIO_WLAN_SDIO_D1_AF 2 - -#define GPIO_WLAN_SDIO_D2 S5PV210_GPG3(5) -#define GPIO_WLAN_SDIO_D2_AF 2 - -#define GPIO_WLAN_SDIO_D3 S5PV210_GPG3(6) -#define GPIO_WLAN_SDIO_D3_AF 2 - -#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) - -#define GPIO_ACC_INT S5PV210_GPH0(1) - -#define GPIO_PS_VOUT S5PV210_GPH0(2) -#define GPIO_PS_VOUT_AF 0xFF - -#define GPIO_BUCK_1_EN_A S5PV210_GPH0(3) - -#define GPIO_BUCK_1_EN_B S5PV210_GPH0(4) - -#define GPIO_BUCK_2_EN S5PV210_GPH0(5) - -#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) -#define GPIO_AP_PMIC_IRQ_AF 0xFF - -#define GPIO_GPH10 S5PV210_GPH1(0) -#define GPIO_DET_35 S5PV210_GPH1(0) -#define GPIO_DET_35_AF 0xF - -#define GPIO_PDA_ACTIVE S5PV210_GPH1(1) - -#define GPIO_GPH12 S5PV210_GPH1(2) -#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) -#define GPIO_nINT_ONEDRAM_AP_AF 0xF - -#define GPIO_GPH14 S5PV210_GPH1(4) -#define GPIO_EAR_SEND_END S5PV210_GPH1(4) -#define GPIO_EAR_SEND_END_AF 0xF - -#define GPIO_GPH15 S5PV210_GPH1(5) - -#define GPIO_GPH16 S5PV210_GPH1(6) - -#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) -#define GPIO_PHONE_ACTIVE_AF 2 +#endif -#define GPIO_KBC0 S5PV210_GPH2(0) -#define GPIO_KBC0_AF 3 -#define GPIO_KBC1 S5PV210_GPH2(1) +#define GPIO_NAND_D4 S5PV210_GPG1(3) +#define GPIO_NAND_D4_AF 3 +#define GPIO_NAND_D5 S5PV210_GPG1(4) +#define GPIO_NAND_D5_AF 3 +#define GPIO_NAND_D6 S5PV210_GPG1(5) +#define GPIO_NAND_D6_AF 3 +#define GPIO_NAND_D7 S5PV210_GPG1(6) +#define GPIO_NAND_D7_AF 3 + +//GPG2 +//------------------------------------------------------------- +#define GPIO_T_FLASH_CLK S5PV210_GPG2(0) +#define GPIO_T_FLASH_CLK_AF 2 +#define GPIO_T_FLASH_CMD S5PV210_GPG2(1) +#define GPIO_T_FLASH_CMD_AF 2 +#define GPIO_ALS_nRST S5PV210_GPG2(2) +#define GPIO_T_FLASH_D0 S5PV210_GPG2(3) +#define GPIO_T_FLASH_D0_AF 2 +#define GPIO_T_FLASH_D1 S5PV210_GPG2(4) +#define GPIO_T_FLASH_D1_AF 2 +#define GPIO_T_FLASH_D2 S5PV210_GPG2(5) +#define GPIO_T_FLASH_D2_AF 2 +#define GPIO_T_FLASH_D3 S5PV210_GPG2(6) +#define GPIO_T_FLASH_D3_AF 2 + +//GPG3 +//------------------------------------------------------------- +#define GPIO_WLAN_SDIO_CLK S5PV210_GPG3(0) +#define GPIO_WLAN_SDIO_CLK_AF 2 +#define GPIO_WLAN_SDIO_CMD S5PV210_GPG3(1) +#define GPIO_WLAN_SDIO_CMD_AF 2 +#define GPIO_WLAN_nRST S5PV210_GPG3(2) +#define GPIO_WLAN_nRST_AF 1 +#define GPIO_WLAN_SDIO_D0 S5PV210_GPG3(3) +#define GPIO_WLAN_SDIO_D0_AF 2 +#define GPIO_WLAN_SDIO_D1 S5PV210_GPG3(4) +#define GPIO_WLAN_SDIO_D1_AF 2 +#define GPIO_WLAN_SDIO_D2 S5PV210_GPG3(5) +#define GPIO_WLAN_SDIO_D2_AF 2 +#define GPIO_WLAN_SDIO_D3 S5PV210_GPG3(6) +#define GPIO_WLAN_SDIO_D3_AF 2 + +//GPH0 +//------------------------------------------------------------- +#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) +#define GPIO_AP_PS_HOLD_AF 1 +#define GPIO_ACC_INT S5PV210_GPH0(1) +#define GPIO_BUCK_1_EN_A S5PV210_GPH0(2) +#define GPIO_BUCK_1_EN_B S5PV210_GPH0(3) +#define GPIO_ACCESSORY_INT S5PV210_GPH0(5) +#define GPIO_ACCESSORY_INT_AF 0xF +#define GPIO_BUCK_2_EN S5PV210_GPH0(4) +#define GPIO_GPH06 S5PV210_GPH0(6) // Rev0.4 +#define GPIO_AP_PMIC_IRQ S5PV210_GPH0(7) +#define GPIO_AP_PMIC_IRQ_AF 0xFF + +//GPH1 +//------------------------------------------------------------- +#define GPIO_GPH10 S5PV210_GPH1(0) +#define GPIO_DET_35 S5PV210_GPH1(0) +#define GPIO_DET_35_AF 0xF +#define GPIO_TA_nCHG S5PV210_GPH1(1) +#define GPIO_GPH12 S5PV210_GPH1(2) +#define GPIO_MHL_INT S5PV210_GPH1(2) +#define GPIO_nINT_ONEDRAM_AP S5PV210_GPH1(3) +#define GPIO_nINT_ONEDRAM_AP_AF 0xF +#define GPIO_GPH14 S5PV210_GPH1(4) +#define GPIO_EAR_SEND_END S5PV210_GPH1(4) +#define GPIO_EAR_SEND_END_AF 0xF +#define NFC_IRQ S5PV210_GPH1(4) +#define GPIO_GPH15 S5PV210_GPH1(5) +#define GPIO_HDMI_HPD S5PV210_GPH1(5) +#define NFC_EN S5PV210_GPH1(5) +#define GPIO_HDMI_HPD_AF 4 +#define GPIO_GPH16 S5PV210_GPH1(6) +#define GPIO_FUEL_ARLT S5PV210_GPH1(6) +#define NFC_FIRM S5PV210_GPH1(6) +#define GPIO_PHONE_ACTIVE S5PV210_GPH1(7) +#define GPIO_PHONE_ACTIVE_AF 2 + +//GPH2** +//------------------------------------------------------------- +#define GPIO_KBC0 S5PV210_GPH2(0) +#define GPIO_KBC0_AF 3 +#define GPIO_GPH20 S5PV210_GPH2(0) +#define GPIO_REMOTE_SENSE_IRQ S5PV210_GPH2(0) + +#if defined(CONFIG_SAMSUNG_P1LN) + +#define GPIO_TOUCH_EN S5PV210_GPH2(1) +#define GPIO_TOUCH_EN_AF 1 + +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) + +#define GPIO_KBC1 S5PV210_GPH2(1) #define GPIO_KBC1_AF 3 -#define GPIO_KBC2 S5PV210_GPH2(2) -#define GPIO_KBC2_AF 3 - -#define GPIO_BT_WAKE S5PV210_GPH2(2) -#define GPIO_WLAN_WAKE S5PV210_GPH2(3) -#define GPIO_WLAN_WAKE_AF 1 - -#define GPIO_KBC_DATA (GPIO_KBC2 + 0x04) - -#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) -#define GPIO_WLAN_HOST_WAKE_AF 0xF - -#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) -#define GPIO_BT_HOST_WAKE_AF 0xF -#define GPIO_nPOWER S5PV210_GPH2(6) - -#define GPIO_JACK_nINT S5PV210_GPH2(7) - -#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPH3(0) - -#define GPIO_KBR1 S5PV210_GPH3(1) -#define GPIO_KBR1_AF 3 +#endif -#define GPIO_MSENSE_IRQ S5PV210_GPH3(2) +#define GPIO_GPH21 S5PV210_GPH2(1) // Rev0.5 +#define GPIO_TOUCH_EN_REV06 S5PV210_GPH2(1) +#define GPIO_TOUCH_EN_REV06_AF 1 +#define GPIO_KBC2 S5PV210_GPH2(2) +#define GPIO_KBC2_AF 3 +#define GPIO_GPH22 S5PV210_GPH2(2) +#define GPIO_GYRO_INT S5PV210_GPH2(2) -#define GPIO_SIM_nDETECT S5PV210_GPH3(3) +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_KBR_DATA (GPIO_KBR1 + 0x04) +#define GPIO_35_INT_TEST S5PV210_GPH2(3) // Rev1.1 (Only latin HW05) -#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) -#define GPIO_T_FLASH_DETECT_AF 0xF +#endif +#define GPIO_TOUCH_KEY_INT S5PV210_GPH2(3) +#define GPIO_GPH23 S5PV210_GPH2(3) +#define GPIO_WLAN_HOST_WAKE S5PV210_GPH2(4) +#define GPIO_WLAN_HOST_WAKE_AF 0xF +#define GPIO_BT_HOST_WAKE S5PV210_GPH2(5) +#define GPIO_BT_HOST_WAKE_AF 0xF +#define GPIO_nPOWER S5PV210_GPH2(6) +#define GPIO_N_POWER S5PV210_GPH2(6) +#define GPIO_N_POWER_AF 2 +#define GPIO_JACK_nINT S5PV210_GPH2(7) +#define GPIO_JACK_INT_N S5PV210_GPH2(7) +#define GPIO_JACK_INT_N_AF 0xFF + +//GPH3 +//------------------------------------------------------------- +#define GPIO_TA_CURRENT_SEL_AP S5PV210_GPH3(0) +#define GPIO_KBR1 S5PV210_GPH3(1) +#define GPIO_KBR1_AF 3 +#define GPIO_MSENSE_IRQ S5PV210_GPH3(2) +#define GPIO_GPH33 S5PV210_GPH3(3) // NC +#define GPIO_SIM_nDETECT S5PV210_GPH3(3) +#define GPIO_T_FLASH_DETECT S5PV210_GPH3(4) +#define GPIO_T_FLASH_DETECT_AF 0xF /* EAR_SEN_END_OPEN */ -#define GPIO_OK_KEY S5PV210_GPH3(5) - -#define GPIO_CP_RST S5PV210_GPH3(7) - -#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) -#define GPIO_CODEC_I2S_CLK_AF 2 - -#define GPIO_GPI1 S5PV210_GPI(1) - -#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) -#define GPIO_CODEC_I2S_WS_AF 2 - -#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) -#define GPIO_CODEC_I3S_DI_AF 2 - -#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) -#define GPIO_CODEC_I3S_DO_AF 2 - -#define GPIO_GPI5 S5PV210_GPI(5) - -#define GPIO_GPI6 S5PV210_GPI(6) - -#define GPIO_MSENSE_SCL_28V S5PV210_GPJ0(0) -#define GPIO_MSENSE_SDA_28V S5PV210_GPJ0(1) - +#define GPIO_OK_KEY S5PV210_GPH3(5) +#define GPIO_GPH35 S5PV210_GPH3(5) // Rev0.5 +#define GPIO_DOCK_INT S5PV210_GPH3(5) +#define GPIO_DOCK_INT_AF 0xF +#define GPIO_GPH36 S5PV210_GPH3(6) // Rev0.4 +#define GPIO_CP_RST S5PV210_GPH3(7) + +//GPI +//------------------------------------------------------------- +#define GPIO_CODEC_I2S_CLK S5PV210_GPI(0) +#define GPIO_CODEC_I2S_CLK_AF 2 +#define GPIO_GPI1 S5PV210_GPI(1) +#define GPIO_CODEC_I2S_WS S5PV210_GPI(2) +#define GPIO_CODEC_I2S_WS_AF 2 +#define GPIO_CODEC_I3S_DI S5PV210_GPI(3) +#define GPIO_CODEC_I3S_DI_AF 2 +#define GPIO_CODEC_I3S_DO S5PV210_GPI(4) +#define GPIO_CODEC_I3S_DO_AF 2 +#define GPIO_GPI5 S5PV210_GPI(5) +#define GPIO_GPI6 S5PV210_GPI(6) + +//GPJ0** +//------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_P1LN) + +#define GPIO_ISDBT_SCL S5PV210_GPJ0(0) +#define GPIO_ISDBT_SDA S5PV210_GPJ0(1) +#define GPIO_ISDBT_CLK S5PV210_GPJ0(2) +#define GPIO_ISDBT_SYNC S5PV210_GPJ0(3) +#define GPIO_ISDBT_VALID S5PV210_GPJ0(4) +#define GPIO_ISDBT_DATA S5PV210_GPJ0(5) +#define GPIO_ISDBT_ERR S5PV210_GPJ0(6) + +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) + +#define GPIO_WLAN_BT_EN S5PV210_GPJ0(0) +#define GPIO_HWREV_MODE3 S5PV210_GPJ0(1) #define GPIO_HWREV_MODE0 S5PV210_GPJ0(2) #define GPIO_HWREV_MODE1 S5PV210_GPJ0(3) #define GPIO_HWREV_MODE2 S5PV210_GPJ0(4) - #define GPIO_TOUCH_INT S5PV210_GPJ0(5) +#define GPIO_TOUCH_INT_AF 0xFF +#define GPIO_HWREV_MODE4 S5PV210_GPJ0(6) -#define GPIO_CAM_MEGA_EN S5PV210_GPJ0(6) +#endif -#define GPIO_HWREV_MODE3 S5PV210_GPJ0(7) +#define GPIO_HWREV_MODE5 S5PV210_GPJ0(7) -#define GPIO_CAM_FLASH_EN_SET S5PV210_GPJ1(0) +//GPJ1** +//------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) -#define GPIO_MASSMEMORY_EN S5PV210_GPJ1(1) // Rev0.6 +#define GPIO_WLAN_BT_EN S5PV210_GPJ1(0) -#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#elif defined(CONFIG_SAMSUNG_P1C) -#define GPIO_FLASH_EN S5PV210_GPJ1(2) -#define GPIO_TOUCH_EN S5PV210_GPJ1(3) -#define GPIO_TOUCH_EN_AF 1 +#define GPIO_PHONE_ON S5PV210_GPJ1(0) -#define GPIO_PS_ON S5PV210_GPJ1(4) +#endif -#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) +#define GPIO_VIBTONE_EN1 S5PV210_GPJ1(1) +#define GPIO_MASSMEMORY_EN S5PV210_GPJ1(1) // Rev0.6 +#define GPIO_CAM_MEGA_EN S5PV210_GPJ1(2) -#define GPIO_OLED_DET S5PV210_GPJ2(2) -#define GPIO_USB_SW_SCL S5PV210_GPJ2(3) +#if defined(CONFIG_SAMSUNG_P1LN) -//#define GPIO_EAR_SEL S5PV210_GPJ2(3) -#define GPIO_FM_INT S5PV210_GPJ2(4) -#define GPIO_FM_RST S5PV210_GPJ2(5) -#define GPIO_LCD_LDO_EN S5PV210_GPJ2(6) +#define GPIO_ISDBT_PWR_EN S5PV210_GPJ1(3) -//#define GPIO_MASSMEMORY_EN S5PV210_GPJ2(7) -#define GPIO_USB_SW_SDA S5PV210_GPJ2(7) +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) -#define _3_TOUCH_SDA_28V S5PV210_GPJ3(0) -#define _3_TOUCH_SCL_28V S5PV210_GPJ3(1) -#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) -#define _3_GPIO_TOUCH_EN_AF 1 -#define GPIO_EAR_ADC_SEL S5PV210_GPJ3(3) -#define GPIO_EAR_ADC_SEL_AF 1 +#define GPIO_TOUCH_EN S5PV210_GPJ1(3) +#define GPIO_TOUCH_EN_AF 1 + +#endif + +#define GPIO_PS_ON S5PV210_GPJ1(4) +#define GPIO_CAM_MEGA_nRST S5PV210_GPJ1(5) -#define GPIO_USB_SDA_28V S5PV210_GPJ3(4) +//GPJ2** +//------------------------------------------------------------- +#define GPIO_CHARGER_SDA_2_8V S5PV210_GPJ2(0) +#define GPIO_CHARGER_SCL_2_8V S5PV210_GPJ2(1) +#define GPIO_OLED_DET S5PV210_GPJ2(2) +#define GPIO_HDMI_EN1 S5PV210_GPJ2(2) +#define GPIO_USB_SW_SCL S5PV210_GPJ2(3) +#define GPIO_EAR_SEL S5PV210_GPJ2(3) +#define GPIO_FM_INT S5PV210_GPJ2(4) +#define GPIO_BT_WAKE S5PV210_GPJ2(4) +#define GPIO_WLAN_WAKE S5PV210_GPJ2(5) +#define GPIO_WLAN_WAKE_AF 1 -#define GPIO_USB_SCL_28V S5PV210_GPJ3(5) +#if defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) -#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) +#define GPIO_FM_RST S5PV210_GPJ2(5) -#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) -#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) +#endif -#define GPIO_MASSMEMORY_EN2_REV06 S5PV210_GPJ4(1) // Rev0.6 +#define GPIO_LCD_LDO_EN S5PV210_GPJ2(6) +#define GPIO_USB_SW_SDA S5PV210_GPJ2(7) -#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) -#define _3_GPIO_TOUCH_INT_AF 0xFF -#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) +//GPJ3** +//------------------------------------------------------------- +#define GPIO_AP_SDA_2_8V S5PV210_GPJ3(0) +#define GPIO_AP_SCL_2_8V S5PV210_GPJ3(1) -#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_MP010 S5PV210_MP01(0) +#define GPIO_ATV_RSTn S5PV210_GPJ3(2) +#define GPIO_ISDBT_PWR_EN_REV10 S5PV210_GPJ3(2) -#define GPIO_DISPLAY_CS S5PV210_MP01(1) +#elif defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) -#define GPIO_RESET_REQ_N S5PV210_MP01(2) +#define _3_GPIO_TOUCH_EN S5PV210_GPJ3(2) +#define _3_GPIO_TOUCH_EN_AF 1 -#define GPIO_OLED_ID S5PV210_MP01(3) +#endif -#define GPIO_AP_NANDCS S5PV210_MP01(4) -#define GPIO_AP_NANDCS_AF 5 +#define GPIO_FUEL_AP_SCL S5PV210_GPJ3(3) +#define GPIO_EAR_ADC_SEL_AF 1 +#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) +#define GPIO_FUEL_AP_SDA S5PV210_GPJ3(4) +#define GPIO_TA_EN S5PV210_GPJ3(5) +#define GPIO_AP_SDA_28V S5PV210_GPJ3(6) +#define AP_I2C_SDA_28V S5PV210_GPJ3(6) +#define GPIO_AP_SCL_28V S5PV210_GPJ3(7) +#define AP_I2C_SCL_28V S5PV210_GPJ3(7) + +//GPJ4 +//------------------------------------------------------------- +#define GPIO_AP_PMIC_SDA S5PV210_GPJ4(0) +#define PMIC_I2C_SDA S5PV210_GPJ4(0) +#define GPIO_MASSMEMORY_EN2_REV06 S5PV210_GPJ4(1) // Rev0.6 +#define _3_GPIO_TOUCH_INT S5PV210_GPJ4(1) +#define _3_GPIO_TOUCH_INT_AF S3C_GPIO_SFN(0xf) +#define GPIO_MICBIAS_EN S5PV210_GPJ4(2) +#define GPIO_AP_PMIC_SCL S5PV210_GPJ4(3) +#define PMIC_I2C_SCL S5PV210_GPJ4(3) + +//MP01** +//------------------------------------------------------------- +// CMC623 +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_DIC_ID S5PV210_MP01(5) +#define GPIO_CMC_SHDN S5PV210_MP01(0) +#define GPIO_CMC_SHDN_AF 2 +#define GPIO_CMC_SLEEP S5PV210_MP01(1) +#define GPIO_CMC_SLEEP_AF 2 -#define GPIO_EAR_MICBIAS_EN S5PV210_MP01(5) +#endif -#define GPIO_MP016 S5PV210_MP01(6) +#define GPIO_MP010 S5PV210_MP01(0) +#define GPIO_DISPLAY_CS S5PV210_MP01(1) +#define GPIO_RESET_REQ_N S5PV210_MP01(2) -#define GPIO_MP017 S5PV210_MP01(7) +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_MP020 S5PV210_MP02(0) +#define GPIO_CMC_RST S5PV210_MP01(3) +#define GPIO_CMC_RST_AF 2 -#define GPIO_MP021 S5PV210_MP02(1) +#endif -#define GPIO_VCC_19V_PDA S5PV210_MP02(2) +#define GPIO_OLED_ID S5PV210_MP01(3) +#define GPIO_AP_NANDCS S5PV210_MP01(4) +#define GPIO_AP_NANDCS_AF 5 +#define GPIO_DIC_ID S5PV210_MP01(5) -#define GPIO_MP023 S5PV210_MP02(3) +#if defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) -#define GPIO_MP030 S5PV210_MP03(0) +#define GPIO_EAR_MICBIAS_EN S5PV210_MP01(5) -#define GPIO_MP031 S5PV210_MP03(1) +#endif -#define GPIO_MP032 S5PV210_MP03(2) +#define GPIO_MP016 S5PV210_MP01(6) +#define GPIO_MP017 S5PV210_MP01(7) + +//MP02 +//------------------------------------------------------------- +#define GPIO_MP020 S5PV210_MP02(0) +#define GPIO_MP021 S5PV210_MP02(1) +#define GPIO_VCC_19V_PDA S5PV210_MP02(2) +#define GPIO_MP023 S5PV210_MP02(3) + +//MP03 +//------------------------------------------------------------- +#define GPIO_MP030 S5PV210_MP03(0) +#define GPIO_MP031 S5PV210_MP03(1) +#define GPIO_MP032 S5PV210_MP03(2) +#define GPIO_PDA_ACTIVE S5PV210_MP03(3) +#define GPIO_VCC_18V_PDA S5PV210_MP03(4) +#define GPIO_CP_nRST S5PV210_MP03(5) +#define GPIO_MP036 S5PV210_MP03(6) +#define GPIO_PCM_SEL S5PV210_MP03(7) + +//MP04** +//------------------------------------------------------------- +#if defined(CONFIG_SAMSUNG_P1LN) + +#define GPIO_GPS_CLK_EN S5PV210_MP04(0) -#define GPIO_MP033 S5PV210_MP03(3) +#endif -#define GPIO_VCC_18V_PDA S5PV210_MP03(4) +#define GPIO_USB_SEL S5PV210_MP04(0) -#define GPIO_CP_nRST S5PV210_MP03(5) +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_MP036 S5PV210_MP03(6) +#define GPIO_TV_CLK_EN S5PV210_MP04(1) -#define GPIO_PCM_SEL S5PV210_MP03(7) +#endif -#define GPIO_USB_SEL S5PV210_MP04(0) +#define GPIO_DISPLAY_CLK S5PV210_MP04(1) +#define GPIO_MP042 S5PV210_MP04(2) +#define GPIO_DISPLAY_SI S5PV210_MP04(3) -#define GPIO_DISPLAY_CLK S5PV210_MP04(1) +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_MP042 S5PV210_MP04(2) +#define GPIO_CMC_EN S5PV210_MP04(4) +#define GPIO_CMC_EN_AF 1 -#define GPIO_DISPLAY_SI S5PV210_MP04(3) +#endif -#define GPIO_MP044 S5PV210_MP04(4) +#define GPIO_MP044 S5PV210_MP04(4) +#define NFC_SCL_18V S5PV210_MP04(4) +#define GPIO_CMC_SDA_18V S5PV210_MP04(5) // Rev0.9 +#define GPIO_LVDS_RST S5PV210_MP04(5) +#define NFC_SDA_18V S5PV210_MP04(5) -#define GPIO_CMC_SDA_18V S5PV210_MP04(5) // Rev0.9 -#define GPIO_LVDS_RST S5PV210_MP04(5) +#if defined(CONFIG_SAMSUNG_P1) || defined(CONFIG_SAMSUNG_P1C) #define GPIO_GPS_CLK_EN S5PV210_MP04(6) -#define GPIO_CMC_SCL_18V S5PV210_MP04(6) // Rev1.2 -#define GPIO_MHL_RST S5PV210_MP04(7) - -#define FUEL_SCL_18V S5PV210_MP05(0) -#define FUEL_SDA_18V S5PV210_MP05(1) +#endif -#define GPIO_EAR_MICBIAS0_EN S5PV210_MP05(1) +#define GPIO_CMC_SCL_18V S5PV210_MP04(6) // Rev1.2 +#define GPIO_MHL_RST S5PV210_MP04(7) -#define GPIO_AP_SCL_18V S5PV210_MP05(2) +//MP05** +//------------------------------------------------------------- +#define FUEL_SCL_18V S5PV210_MP05(0) +#define FUEL_SDA_18V S5PV210_MP05(1) +#define GPIO_EAR_MICBIAS0_EN S5PV210_MP05(1) +#define GPIO_AP_SCL_18V S5PV210_MP05(2) +#define GPIO_AP_SDA_18V S5PV210_MP05(3) +#define GPIO_MP054 S5PV210_MP05(4) +#define GPIO_LVDS_SHDN S5PV210_MP05(4) -#define GPIO_AP_SDA_18V S5PV210_MP05(3) +#if defined(CONFIG_SAMSUNG_P1LN) -#define GPIO_MP054 S5PV210_MP05(4) -#define GPIO_LVDS_SHDN S5PV210_MP05(4) +#define GPIO_EAR_MICBIAS_EN S5PV210_MP05(5) -#define GPIO_MLCD_RST S5PV210_MP05(5) +#endif -#define GPIO_MP056 S5PV210_MP05(6) +#define GPIO_MLCD_RST S5PV210_MP05(5) -#define GPIO_UART_SEL S5PV210_MP05(7) +#if defined(CONFIG_SAMSUNG_P1LN) -#define AP_I2C_SDA S5PV210_MP05(3) -#define AP_I2C_SCL S5PV210_MP05(2) -#define AP_I2C_SDA_28V S5PV210_GPJ3(6) -#define AP_I2C_SCL_28V S5PV210_GPJ3(7) +#define GPIO_CMC_BYPASS S5PV210_MP05(6) +#define GPIO_CMC_BYPASS_AF 2 -#define NFC_SCL_18V S5PV210_MP04(4) -#define NFC_SDA_18V S5PV210_MP04(5) -#define NFC_IRQ S5PV210_GPH1(4) -#define NFC_EN S5PV210_GPH1(5) -#define NFC_FIRM S5PV210_GPH1(6) +#endif -#define PMIC_I2C_SDA S5PV210_GPJ4(0) -#define PMIC_I2C_SCL S5PV210_GPJ4(3) +#define GPIO_MP056 S5PV210_MP05(6) +#define GPIO_UART_SEL S5PV210_MP05(7) +#define AP_I2C_SDA S5PV210_MP05(3) +#define AP_I2C_SCL S5PV210_MP05(2) -#define GPIO_TOUCH_INT S5PV210_GPJ0(5) -#define GPIO_TOUCH_INT_AF 0xFF +#define GPIO_KBC_DATA (GPIO_KBC2 + 0x04) +#define GPIO_KBR_DATA (GPIO_KBR1 + 0x04) -#define GPIO_TOUCH_RST S5PV210_GPB(6) -#define GPIO_TOUCH_ST_AF 1 - -#define GPIO_BT_RXD S5PV210_GPA0(0) -#define GPIO_BT_RXD_AF 2 -#define GPIO_BT_TXD S5PV210_GPA0(1) -#define GPIO_BT_TXD_AF 2 -#define GPIO_BT_CTS S5PV210_GPA0(2) -#define GPIO_BT_CTS_AF 2 -#define GPIO_BT_RTS S5PV210_GPA0(3) -#define GPIO_BT_RTS_AF 2 - -#define GPIO_GPS_RXD S5PV210_GPA0(4) -#define GPIO_GPS_RXD_AF 2 -#define GPIO_GPS_TXD S5PV210_GPA0(5) -#define GPIO_GPS_TXD_AF 2 -#define GPIO_GPS_CTS S5PV210_GPA0(6) -#define GPIO_GPS_CTS_AF 2 -#define GPIO_GPS_RTS S5PV210_GPA0(7) -#define GPIO_GPS_RTS_AF 2 - -#define GPIO_AP_RXD S5PV210_GPA1(0) -#define GPIO_AP_RXD_AF 2 -#define GPIO_AP_TXD S5PV210_GPA1(1) -#define GPIO_AP_TXD_AF 2 - -#define GPIO_FLM_RXD S5PV210_GPA1(2) -#define GPIO_FLM_RXD_AF 2 -#define GPIO_FLM_TXD S5PV210_GPA1(3) -#define GPIO_FLM_TXD_AF 2 - -#define GPIO_AP_PS_HOLD S5PV210_GPH0(0) -#define GPIO_AP_PS_HOLD_AF 1 - -#define GPIO_N_POWER S5PV210_GPH2(6) -#define GPIO_N_POWER_AF 2 - -#define GPIO_JACK_INT_N S5PV210_GPH2(7) -#define GPIO_JACK_INT_N_AF 0xFF - -#define _3_GPIO_TOUCH_CE S5PV210_GPJ3(3) #endif /* end of __GPIO_P1_H_ */ diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index 16b38f1..70e1330 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h @@ -228,6 +228,10 @@ enum s5p_gpio_number { #include <plat/gpio-cfg.h> +#if defined (CONFIG_SAMSUNG_P1LN) +#include "gpio-p1.h" +#endif /* P1L or P1N */ + extern int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int to); extern s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin); diff --git a/arch/arm/mach-s5pv210/include/mach/mach-p1.h b/arch/arm/mach-s5pv210/include/mach/mach-p1.h new file mode 100644 index 0000000..765994f --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/mach-p1.h @@ -0,0 +1,23 @@ +/* linux/arch/arm/mach-s5pv210/include/mach/mach-p1.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#ifndef __MACH_P1_H_ +#define __MACH_P1_H_ + +#define P1_HWREV_REV06 0x0C +#define P1_HWREV_REV07 0x0D +#define P1_HWREV_REV08 0x0E +#define P1_HWREV_REV09 0x0F +#define P1_HWREV_REV10 0x10 +#define P1_HWREV_REV11 0x11 +#define P1_HWREV_REV12 0x12 + +extern unsigned int HWREV; + +#endif // __MACH_P1_H_ diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 704e192..dfecbd8 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -209,6 +209,13 @@ #define S5P_PA_CEC S5PV210_PA_CEC #define S5P_SZ_CEC SZ_4K +#if defined(CONFIG_VIDEO_TSI) +/* s3c-tsi */ +#define S5PV210_PA_TSI (0xEB400000) +#define S5P_PA_TSI S5PV210_PA_TSI +#define S5P_SZ_TSI SZ_256 +#endif + /* TVOUT */ #define S5PV210_PA_TVENC (0xF9000000) #define S5P_PA_TVENC S5PV210_PA_TVENC diff --git a/arch/arm/mach-s5pv210/include/mach/param.h b/arch/arm/mach-s5pv210/include/mach/param.h index dbba308..6de0509 100644 --- a/arch/arm/mach-s5pv210/include/mach/param.h +++ b/arch/arm/mach-s5pv210/include/mach/param.h @@ -1,89 +1,93 @@ -
-/*
- * Parameter Infomation
- */
-
-#ifndef ASM_MACH_PARAM_H
-#define ASM_MACH_PARAM_H
-
-#define PARAM_MAGIC 0x72726624
-#define PARAM_VERSION 0x13 /* Rev 1.3 */
-#define PARAM_STRING_SIZE 1024 /* 1024 Characters */
-
-#define MAX_PARAM 20
-#define MAX_STRING_PARAM 5
-
-/* Default Parameter Values */
-
-#define SERIAL_SPEED 7 /* Baudrate */
-#define LCD_LEVEL 0x061 /* Backlight Level */
-#define BOOT_DELAY 0 /* Boot Wait Time */
-#define LOAD_RAMDISK 0 /* Enable Ramdisk Loading */
-#define SWITCH_SEL 1 /* Switch Setting (UART[1], USB[0]) */
-#define PHONE_DEBUG_ON 0 /* Enable Phone Debug Mode */
-#define LCD_DIM_LEVEL 0x011 /* Backlight Dimming Level */
-#define LCD_DIM_TIME 0
-#define MELODY_MODE 0 /* Melody Mode */
-#define REBOOT_MODE 0 /* Reboot Mode */
-#define NATION_SEL 0 /* Language Configuration */
-#define LANGUAGE_SEL 0
-#define SET_DEFAULT_PARAM 0 /* Set Param to Default */
-#define VERSION_LINE "I8315XXIE00" /* Set Image Info */
-#define COMMAND_LINE "console=ttySAC2,115200"
-#define BOOT_VERSION " version=Sbl(1.0.0) "
-
-typedef enum {
- __SERIAL_SPEED,
- __LOAD_RAMDISK,
- __BOOT_DELAY,
- __LCD_LEVEL,
- __SWITCH_SEL,
- __PHONE_DEBUG_ON,
- __LCD_DIM_LEVEL,
- __LCD_DIM_TIME,
- __MELODY_MODE,
- __REBOOT_MODE,
- __NATION_SEL,
- __LANGUAGE_SEL,
- __SET_DEFAULT_PARAM,
- __PARAM_INT_13, /* Reserved. */
- __PARAM_INT_14, /* Reserved. */
- __VERSION,
- __CMDLINE,
- __PARAM_STR_2,
- __PARAM_STR_3, /* Reserved. */
- __PARAM_STR_4 /* Reserved. */
-} param_idx;
-
-typedef struct _param_int_t {
- param_idx ident;
- int value;
-} param_int_t;
-
-typedef struct _param_str_t {
- param_idx ident;
- char value[PARAM_STRING_SIZE];
-} param_str_t;
-
-typedef struct {
- int param_magic;
- int param_version;
- param_int_t param_list[MAX_PARAM - MAX_STRING_PARAM];
- param_str_t param_str_list[MAX_STRING_PARAM];
-} status_t;
-
-/* REBOOT_MODE */
-#define REBOOT_MODE_NONE 0
-#define REBOOT_MODE_DOWNLOAD 1
-#define REBOOT_MODE_CHARGING 3
-#define REBOOT_MODE_RECOVERY 4
-#define REBOOT_MODE_ARM11_FOTA 5
-#define REBOOT_MODE_ARM9_FOTA 6
-
-extern void (*sec_set_param_value)(int idx, void *value);
-extern void (*sec_get_param_value)(int idx, void *value);
-
-#define USB_SEL_MASK (1 << 0)
-#define UART_SEL_MASK (1 << 1)
-
-#endif /* ASM_MACH_PARAM_H */
+ +/* + * Parameter Infomation + */ + +#ifndef ASM_MACH_PARAM_H +#define ASM_MACH_PARAM_H + +#define PARAM_MAGIC 0x72726624 +#define PARAM_VERSION 0x13 /* Rev 1.3 */ +#define PARAM_STRING_SIZE 1024 /* 1024 Characters */ + +#define MAX_PARAM 20 +#define MAX_STRING_PARAM 5 + +/* Default Parameter Values */ + +#define SERIAL_SPEED 7 /* Baudrate */ +#define LCD_LEVEL 0x061 /* Backlight Level */ +#define BOOT_DELAY 0 /* Boot Wait Time */ +#define LOAD_RAMDISK 0 /* Enable Ramdisk Loading */ +#define SWITCH_SEL 1 /* Switch Setting (UART[1], USB[0]) */ +#define PHONE_DEBUG_ON 0 /* Enable Phone Debug Mode */ +#define LCD_DIM_LEVEL 0x011 /* Backlight Dimming Level */ +#define LCD_DIM_TIME 0 +#define MELODY_MODE 0 /* Melody Mode */ +#define REBOOT_MODE 0 /* Reboot Mode */ +#define NATION_SEL 0 /* Language Configuration */ +#define LANGUAGE_SEL 0 +#define SET_DEFAULT_PARAM 0 /* Set Param to Default */ +#define VERSION_LINE "I8315XXIE00" /* Set Image Info */ +#ifdef CONFIG_FIQ +#define COMMAND_LINE "console=ttyFIQ0,115200" +#else +#define COMMAND_LINE "console=ttySAC2,115200" +#endif +#define BOOT_VERSION " version=Sbl(1.0.0) " + +typedef enum { + __SERIAL_SPEED, + __LOAD_RAMDISK, + __BOOT_DELAY, + __LCD_LEVEL, + __SWITCH_SEL, + __PHONE_DEBUG_ON, + __LCD_DIM_LEVEL, + __LCD_DIM_TIME, + __MELODY_MODE, + __REBOOT_MODE, + __NATION_SEL, + __LANGUAGE_SEL, + __SET_DEFAULT_PARAM, + __PARAM_INT_13, /* Reserved. */ + __PARAM_INT_14, /* Reserved. */ + __VERSION, + __CMDLINE, + __PARAM_STR_2, + __PARAM_STR_3, /* Reserved. */ + __PARAM_STR_4 /* Reserved. */ +} param_idx; + +typedef struct _param_int_t { + param_idx ident; + int value; +} param_int_t; + +typedef struct _param_str_t { + param_idx ident; + char value[PARAM_STRING_SIZE]; +} param_str_t; + +typedef struct { + int param_magic; + int param_version; + param_int_t param_list[MAX_PARAM - MAX_STRING_PARAM]; + param_str_t param_str_list[MAX_STRING_PARAM]; +} status_t; + +/* REBOOT_MODE */ +#define REBOOT_MODE_NONE 0 +#define REBOOT_MODE_DOWNLOAD 1 +#define REBOOT_MODE_CHARGING 3 +#define REBOOT_MODE_RECOVERY 4 +#define REBOOT_MODE_ARM11_FOTA 5 +#define REBOOT_MODE_ARM9_FOTA 6 + +extern void (*sec_set_param_value)(int idx, void *value); +extern void (*sec_get_param_value)(int idx, void *value); + +#define USB_SEL_MASK (1 << 0) +#define UART_SEL_MASK (1 << 1) + +#endif /* ASM_MACH_PARAM_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index d5d51cd..91d212c 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -83,7 +83,7 @@ #define S5P_MIXER_OUT_SEL S5P_CLKREG(0x7004) #define S5P_EPLL_EN (1<<31) -#define S5P_EPLL_MASK 0xffffffff +#define S5P_EPLL_MASK 0xffffffff #define S5P_EPLLVAL(_v,_m,_p,_s) ((_v) << 27 | (_m) << 16 | ((_p) << 8) | ((_s))) #define S5P_EPLL_MASK_VSEL (0x1<<27) @@ -136,7 +136,7 @@ #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) /* IP Clock Gate 0 Registers */ -#define S5P_CLKGATE_IP0_CSIS (1<<31) +#define S5P_CLKGATE_IP0_CSIS (1<<31) #define S5P_CLKGATE_IP0_IPC (1<<30) #define S5P_CLKGATE_IP0_ROTATOR (1<<29) #define S5P_CLKGATE_IP0_JPEG (1<<28) @@ -154,7 +154,7 @@ #define S5P_CLKGATE_IP0_DMC0 (1<<0) /* IP Clock Gate 1 Registers */ -#define S5P_CLKGATE_IP1_NFCON (1<<28) +#define S5P_CLKGATE_IP1_NFCON (1<<28) #define S5P_CLKGATE_IP1_SROMC (1<<26) #define S5P_CLKGATE_IP1_CFCON (1<<25) #define S5P_CLKGATE_IP1_NANDXL (1<<24) @@ -169,7 +169,7 @@ #define S5P_CLKGATE_IP1_FIMD (1<<0) /* IP Clock Gate 2 Registers */ -#define S5P_CLKGATE_IP2_TZIC3 (1<<31) +#define S5P_CLKGATE_IP2_TZIC3 (1<<31) #define S5P_CLKGATE_IP2_TZIC2 (1<<30) #define S5P_CLKGATE_IP2_TZIC1 (1<<29) #define S5P_CLKGATE_IP2_TZIC0 (1<<28) @@ -215,7 +215,7 @@ #define S5P_CLKGATE_IP3_I2C0 (1<<7) #define S5P_CLKGATE_IP3_I2S2 (1<<6) #define S5P_CLKGATE_IP3_I2S1 (1<<5) -#define S5P_CLKGATE_IP3_I2S0 (1<<4) +#define S5P_CLKGATE_IP3_I2S0 (1<<4) #define S5P_CLKGATE_IP3_AC97 (1<<1) #define S5P_CLKGATE_IP3_SPDIF (1<<0) @@ -372,6 +372,9 @@ #define S5P_OTHERS_RET_UART (1 << 28) #define S5P_OTHERS_USB_SIG_MASK (1 << 16) +/* MIPI */ +#define S5P_MIPI_DPHY_EN (3) + /* S5P_DAC_CONTROL */ #define S5P_DAC_ENABLE (1) #define S5P_DAC_DISABLE (0) diff --git a/arch/arm/mach-s5pv210/include/mach/regs-tsi.h b/arch/arm/mach-s5pv210/include/mach/regs-tsi.h new file mode 100644 index 0000000..7f16748 --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-tsi.h @@ -0,0 +1,163 @@ +/* arch/arm/plat-s3c/include/plat/regs-tsi.h + * + * Copyright (c) 2004 Samsung + * + * This program is free software; yosu can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S5PC110 TSI registers +*/ +#ifndef __ASM_ARCH_REGS_TSI_H +#define __ASM_ARCH_REGS_TSI_H "regs-tsi.h" + +#define S3C_TSIREG(x) (x) + +#define S3C_TS_CLKCON S3C_TSIREG(0x00) +#define S3C_TS_CON S3C_TSIREG(0x04) +#define S3C_TS_SYNC S3C_TSIREG(0x08) +#define S3C_TS_CNT S3C_TSIREG(0x0C) +#define S3C_TS_BASE S3C_TSIREG(0x10) +#define S3C_TS_SIZE S3C_TSIREG(0x14) +#define S3C_TS_CADDR S3C_TSIREG(0x18) +#define S3C_TS_INTMASK S3C_TSIREG(0x1C) +#define S3C_TS_INT S3C_TSIREG(0x20) +#define S3C_TS_PID0 S3C_TSIREG(0x24) +#define S3C_TS_PID1 S3C_TSIREG(0x28) +#define S3C_TS_PID2 S3C_TSIREG(0x2C) +#define S3C_TS_PID3 S3C_TSIREG(0x30) +#define S3C_TS_PID4 S3C_TSIREG(0x34) +#define S3C_TS_PID5 S3C_TSIREG(0x38) +#define S3C_TS_PID6 S3C_TSIREG(0x3C) +#define S3C_TS_PID7 S3C_TSIREG(0x40) +#define S3C_TS_PID8 S3C_TSIREG(0x44) +#define S3C_TS_PID9 S3C_TSIREG(0x48) +#define S3C_TS_PID10 S3C_TSIREG(0x4C) +#define S3C_TS_PID11 S3C_TSIREG(0x50) +#define S3C_TS_PID12 S3C_TSIREG(0x54) +#define S3C_TS_PID13 S3C_TSIREG(0x58) +#define S3C_TS_PID14 S3C_TSIREG(0x5C) +#define S3C_TS_PID15 S3C_TSIREG(0x60) +#define S3C_TS_PID16 S3C_TSIREG(0x64) +#define S3C_TS_PID17 S3C_TSIREG(0x68) +#define S3C_TS_PID18 S3C_TSIREG(0x6C) +#define S3C_TS_PID19 S3C_TSIREG(0x70) +#define S3C_TS_PID20 S3C_TSIREG(0x74) +#define S3C_TS_PID21 S3C_TSIREG(0x78) +#define S3C_TS_PID22 S3C_TSIREG(0x7C) +#define S3C_TS_PID23 S3C_TSIREG(0x80) +#define S3C_TS_PID24 S3C_TSIREG(0x84) +#define S3C_TS_PID25 S3C_TSIREG(0x88) +#define S3C_TS_PID26 S3C_TSIREG(0x8C) +#define S3C_TS_PID27 S3C_TSIREG(0x90) +#define S3C_TS_PID28 S3C_TSIREG(0x94) +#define S3C_TS_PID29 S3C_TSIREG(0x98) +#define S3C_TS_PID30 S3C_TSIREG(0x9C) +#define S3C_TS_PID31 S3C_TSIREG(0xA0) +#define S3C_TS_BYTE_SWAP S3C_TSIREG(0xBC) + +#define TS_TIMEOUT_CNT_MAX (0x00FFFFFF) +#define TS_NUM_PKT (4) +#define TS_PKT_SIZE 47 +#define TS_PKT_BUF_SIZE (TS_PKT_SIZE*TS_NUM_PKT) +#define TSI_CLK_START 1 +#define TSI_CLK_STOP 0 + + + + +/*bit definitions*/ +//CLKCON + +#define S3C_TSI_ON (0x1<<0) +#define S3C_TSI_ON_MASK (0x1<<0) +#define S3C_TSI_BLK_READY (0x1<<1) + +//TS_CON +#define S3C_TSI_SWRESET (0x1 << 31) +#define S3C_TSI_SWRESET_MASK (0x1<< 31) +#define S3C_TSI_CLKFILTER_ON (0x1 << 30) +#define S3C_TSI_CLKFILTER_MASK (0x1 << 30) +#define S3C_TSI_CLKFILTER_SHIFT 30 +#define S3C_TSI_BURST_LEN_0 (0x0 << 28) +#define S3C_TSI_BURST_LEN_4 (0x1 << 28) +#define S3C_TSI_BURST_LEN_8 (0x2 << 28) +#define S3C_TSI_BURST_LEN_MASK (0x3 << 28) +#define S3C_TSI_BURST_LEN_SHIFT (28) + +#define S3C_TSI_OUT_BUF_FULL_INT_ENA (0x1 << 27) +#define S3C_TSI_OUT_BUF_FULL_INT_MASK (0x1 << 27) +#define S3C_TSI_INT_FIFO_FULL_INT_ENA (0x1 << 26) +#define S3C_TSI_INT_FIFO_FULL_INT_ENA_MASK (0x1 << 26) + +#define S3C_TSI_SYNC_MISMATCH_INT_SKIP (0x2 << 24) +#define S3C_TSI_SYNC_MISMATCH_INT_STOP (0x3 << 24) +#define S3C_TSI_SYNC_MISMATCH_INT_MASK (0x3 << 24) + +#define S3C_TSI_PSUF_INT_SKIP (0x2 << 22) +#define S3C_TSI_PSUF_INT_STOP (0x3 << 22) +#define S3C_TSI_PSUF_INT_MASK (0x3 << 22) + +#define S3C_TSI_PSOF_INT_SKIP (0x2 << 20) +#define S3C_TSI_PSOF_INT_STOP (0x3 << 20) +#define S3C_TSI_PSOF_INT_MASK (0x3 << 20) + +#define S3C_TSI_TS_CLK_TIME_OUT_INT (0x1 << 19) +#define S3C_TSI_TS_CLK_TIME_OUT_INT_MASK (0x1 << 19) + +#define S3C_TSI_TS_ERROR_SKIP_SIZE_INT (4<<16) +#define S3C_TSI_TS_ERROR_STOP_SIZE_INT (5<<16) +#define S3C_TSI_TS_ERROR_SKIP_PKT_INT (6<<16) +#define S3C_TSI_TS_ERROR_STOP_PKT_INT (7<<16) +#define S3C_TSI_TS_ERROR_MASK (7<<16) +#define S3C_TSI_PAD_PATTERN_SHIFT (8) +#define S3C_TSI_PID_FILTER_ENA (1 << 7) +#define S3C_TSI_PID_FILTER_MASK (1 << 7) +#define S3C_TSI_PID_FILTER_SHIFT (7) +#define S3C_TSI_ERROR_ACTIVE_LOW (1<<6) +#define S3C_TSI_ERROR_ACTIVE_HIGH (0<<6) +#define S3C_TSI_ERROR_ACTIVE_MASK (1<<6) + +#define S3C_TSI_DATA_BYTE_ORDER_M2L (0 << 5) +#define S3C_TSI_DATA_BYTE_ORDER_L2M (1 << 5) +#define S3C_TSI_DATA_BYTE_ORDER_MASK (1 << 5) +#define S3C_TSI_DATA_BYTE_ORDER_SHIFT (5) +#define S3C_TSI_TS_VALID_ACTIVE_HIGH (0<<4) +#define S3C_TSI_TS_VALID_ACTIVE_LOW (1<<4) +#define S3C_TSI_TS_VALID_ACTIVE_MASK (1<<4) + +#define S3C_TSI_SYNC_ACTIVE_HIGH (0 << 3) +#define S3C_TSI_SYNC_ACTIVE_LOW (1 << 3) +#define S3C_TSI_SYNC_ACTIVE_MASK (1 << 3) + +#define S3C_TSI_CLK_INVERT_HIGH (0 << 2) +#define S3C_TSI_CLK_INVERT_LOW (1 << 2) +#define S3C_TSI_CLK_INVERT_MASK (1 << 2) + +//TS_SYNC +#define S3C_TSI_SYNC_DET_MODE_TS_SYNC8 (0<<0) +#define S3C_TSI_SYNC_DET_MODE_TS_SYNC1 (1<<0) +#define S3C_TSI_SYNC_DET_MODE_TS_SYNC_BYTE (2<<0) +#define S3C_TSI_SYNC_DET_MODE_TS_SYNC_MASK (3<<0) + + +// TS_INT_MASK +#define S3C_TSI_DMA_COMPLETE_ENA (1 <<7) +#define S3C_TSI_OUTPUT_BUF_FULL_ENA (1 <<6) +#define S3C_TSI_INT_FIFO_FULL_ENA (1 <<5) +#define S3C_TSI_SYNC_MISMATCH_ENA (1 <<4) +#define S3C_TSI_PKT_SIZE_UNDERFLOW_ENA (1 <<3) +#define S3C_TSI_PKT_SIZE_OVERFLOW_ENA (1 <<2) +#define S3C_TSI_TS_CLK_ENA (1 <<1) +#define S3C_TSI_TS_ERROR_ENA (1 <<0) + +//TS_INT_FLAG +#define S3C_TSI_DMA_COMPLETE (1<<7) +#define S3C_TSI_OUT_BUF_FULL (1<<6) +#define S3C_TSI_INT_FIFO_FULL (1<<5) +#define S3C_TSI_SYNC_MISMATCH (1<<4) +#define S3C_TSI_PKT_UNDERFLOW (1<<3) +#define S3C_TSI_PKT_OVERFLOW (1<<2) +#define S3C_TSI_PKT_CLK (1<<1) +#define S3C_TSI_ERROR (1<<0) +#endif /* __ASM_ARCH_REGS_TSI_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/sec_jack.h b/arch/arm/mach-s5pv210/include/mach/sec_jack.h new file mode 100644 index 0000000..a7916ad --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/sec_jack.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2008 Samsung Electronics, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_SEC_HEADSET_H +#define __ASM_ARCH_SEC_HEADSET_H + +#define SEC_HEADSET_ADC_CHANNEL 3 +enum +{ + SEC_JACK_NO_DEVICE = 0x0, + SEC_HEADSET_4_POLE_DEVICE = 0x01 << 0, + SEC_HEADSET_3_POLE_DEVICE = 0x01 << 1, +//doesn't use below 3 dev. + SEC_TTY_DEVICE = 0x01 << 2, + SEC_FM_HEADSET = 0x01 << 3, + SEC_FM_SPEAKER = 0x01 << 4, + SEC_TVOUT_DEVICE = 0x01 << 5, + SEC_UNKNOWN_DEVICE = 0x01 << 6, +}; + +enum +{ + JACK_DETACHED = 0x0, + JACK_ATTACHED = 0x1, +}; + +struct sec_gpio_info +{ + int eint; + int gpio; + int gpio_af; + int low_active; +}; + +struct sec_jack_port +{ + struct sec_gpio_info det_jack; + struct sec_gpio_info send_end; +}; + +struct sec_jack_platform_data +{ + struct sec_jack_port *port; + int nheadsets; +}; + + +#endif diff --git a/arch/arm/mach-s5pv210/include/mach/sec_switch.h b/arch/arm/mach-s5pv210/include/mach/sec_switch.h index c1e8f69..8cc3a63 100644 --- a/arch/arm/mach-s5pv210/include/mach/sec_switch.h +++ b/arch/arm/mach-s5pv210/include/mach/sec_switch.h @@ -16,18 +16,34 @@ #define __ASM_ARCH_SEC_SWITCH_H struct sec_switch_platform_data { +#ifdef CONFIG_MACH_P1 + int (*get_regulator) (void); + void (*set_regulator) (int mode); + void (*set_switch_status) (int val); +#endif +#ifdef CONFIG_MACH_ARIES void (*set_vbus_status) (u8 mode); void (*set_usb_gadget_vbus) (bool en); +#endif int (*get_cable_status) (void); int (*get_phy_init_status) (void); }; #define SWITCH_MODEM 0 #define SWITCH_PDA 1 +#ifdef CONFIG_MACH_P1 +enum { + AP_VBUS_ON = 0, + CP_VBUS_ON, + AP_VBUS_OFF, +}; +#endif +#ifdef CONFIG_MACH_ARIES #define USB_VBUS_ALL_OFF 0 #define USB_VBUS_CP_ON 1 #define USB_VBUS_AP_ON 2 #define USB_VBUS_ALL_ON 3 +#endif #endif diff --git a/arch/arm/mach-s5pv210/mach-p1.c b/arch/arm/mach-s5pv210/mach-p1.c new file mode 100644 index 0000000..5628e44 --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-p1.c @@ -0,0 +1,7769 @@ +/* linux/arch/arm/mach-s5pv210/mach-p1.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/gpio.h> +#include <linux/videodev2.h> +#include <linux/i2c.h> +#include <linux/i2c-gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/mfd/max8998.h> +#include <linux/smb136_charger.h> +#include <linux/sec_battery.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/usb/ch9.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/clk.h> +#include <linux/usb/ch9.h> +#include <linux/input.h> +#include <linux/irq.h> +#include <linux/skbuff.h> +#include <linux/console.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <mach/gpio.h> +#include <mach/gpio-p1.h> +#include <mach/mach-p1.h> +#include <mach/sec_switch.h> +#include <mach/adc.h> +#include <mach/param.h> +#include <mach/system.h> + +#ifdef CONFIG_SEC_HEADSET +#include <mach/sec_jack.h> +#endif + +#include <linux/usb/gadget.h> +#include <linux/fsa9480.h> +#include <linux/notifier.h> +#include <linux/reboot.h> +#include <linux/wlan_plat.h> +#include <linux/mfd/wm8994/wm8994_pdata.h> + +#ifdef CONFIG_ANDROID_PMEM +#include <linux/android_pmem.h> +#endif + +#include <plat/media.h> +#include <mach/media.h> + +#ifdef CONFIG_S5PV210_POWER_DOMAIN +#include <mach/power-domain.h> +#endif +#include <mach/cpu-freq-v210.h> + +#ifdef CONFIG_VIDEO_ISX005 +#include <media/isx005_platform.h> +#endif +#ifdef CONFIG_VIDEO_S5K6AAFX +#include <media/s5k6aafx_platform.h> +#endif +#ifdef CONFIG_VIDEO_S5K5CCGX +#include <media/s5k5ccgx_platform.h> +#endif +#ifdef CONFIG_VIDEO_NM6XX +#include <media/nm6xx_platform.h> +#endif + +#include <plat/regs-serial.h> +#include <plat/s5pv210.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/fb.h> +#include <plat/mfc.h> +#include <plat/iic.h> +#include <plat/pm.h> +#include <plat/s5p-time.h> + +#include <plat/sdhci.h> +#include <plat/fimc.h> +#include <plat/jpeg.h> +#include <plat/clock.h> +#include <plat/regs-otg.h> +#include <linux/bh1721.h> +#include <linux/i2c/l3g4200d.h> +#include <../../../drivers/input/misc/bma020.h> +#include <../../../drivers/video/samsung/s3cfb.h> +#include <linux/max17042_battery.h> +#include <linux/switch.h> + +#if defined(CONFIG_KEYBOARD_GPIO) +#include <linux/gpio_keys.h> +#else +#if defined(CONFIG_INPUT_GPIO) +#include <linux/gpio_event.h> +#endif +#endif + +#if defined(CONFIG_DVFS_LIMIT) +#include <mach/cpu-freq-v210.h> +#endif + +extern void s3c_setup_uart_cfg_gpio(unsigned char port); + +struct class *sec_class; +EXPORT_SYMBOL(sec_class); + +struct device *switch_dev; +EXPORT_SYMBOL(switch_dev); + +void (*sec_set_param_value)(int idx, void *value); +EXPORT_SYMBOL(sec_set_param_value); + +void (*sec_get_param_value)(int idx, void *value); +EXPORT_SYMBOL(sec_get_param_value); + +#define KERNEL_REBOOT_MASK 0xFFFFFFFF +#define REBOOT_MODE_FAST_BOOT 7 + + +#ifdef CONFIG_DHD_USE_STATIC_BUF + +#define PREALLOC_WLAN_SEC_NUM 4 +#define PREALLOC_WLAN_BUF_NUM 160 +#define PREALLOC_WLAN_SECTION_HEADER 24 + +#define WLAN_SECTION_SIZE_0 (PREALLOC_WLAN_BUF_NUM * 128) +#define WLAN_SECTION_SIZE_1 (PREALLOC_WLAN_BUF_NUM * 128) +#define WLAN_SECTION_SIZE_2 (PREALLOC_WLAN_BUF_NUM * 512) +#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024) + +#define WLAN_SKB_BUF_NUM 16 + +static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM]; +EXPORT_SYMBOL(wlan_static_skb); + +struct wifi_mem_prealloc { + void *mem_ptr; + unsigned long size; +}; + +#endif + + +struct sec_battery_callbacks *callbacks; +struct max17042_callbacks *max17042_cb; +static enum cable_type_t set_cable_status; +static enum charging_status_type_t charging_status; +static int fsa9480_init_flag = 0; +static int sec_switch_status = 0; +static int sec_switch_inited = 0; +static bool fsa9480_jig_status = 0; +static bool ap_vbus_disabled = 0; + +int sec_switch_set_regulator(int mode); +void otg_phy_init(void); + +extern bool keyboard_enable; + +static int p1_notifier_call(struct notifier_block *this, + unsigned long code, void *_cmd) +{ + int mode = REBOOT_MODE_NONE; + + if ((code == SYS_RESTART) && _cmd) { + if (!strcmp((char *)_cmd, "recovery")) + mode = 2; // It's not REBOOT_MODE_RECOVERY, blame Samsung + else + mode = REBOOT_MODE_NONE; + } + __raw_writel(mode, S5P_INFORM6); + + if(code != SYS_POWER_OFF) { + if(sec_set_param_value) { + sec_set_param_value(__REBOOT_MODE, &mode); + } + } + + return NOTIFY_DONE; +} + +static struct notifier_block p1_reboot_notifier = { + .notifier_call = p1_notifier_call, +}; + +#if defined(CONFIG_PHONE_P1_GSM) +static void gps_gpio_init(void) +{ + struct device *gps_dev; + + gps_dev = device_create(sec_class, NULL, 0, NULL, "gps"); + if (IS_ERR(gps_dev)) { + pr_err("Failed to create device(gps)!\n"); + goto err; + } + + gpio_request(GPIO_GPS_nRST, "GPS_nRST"); /* XMMC3CLK */ + s3c_gpio_setpull(GPIO_GPS_nRST, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_nRST, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_GPS_nRST, 1); + + gpio_request(GPIO_GPS_PWR_EN, "GPS_PWR_EN"); /* XMMC3CLK */ + s3c_gpio_setpull(GPIO_GPS_PWR_EN, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_PWR_EN, S3C_GPIO_OUTPUT); + gpio_direction_output(GPIO_GPS_PWR_EN, 0); + + s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP); + gpio_export(GPIO_GPS_nRST, 1); + gpio_export(GPIO_GPS_PWR_EN, 1); + + gpio_export_link(gps_dev, "GPS_nRST", GPIO_GPS_nRST); + gpio_export_link(gps_dev, "GPS_PWR_EN", GPIO_GPS_PWR_EN); + + err: + return; +} +#endif + +static void uart_switch_init(void) +{ + int ret; + struct device *uartswitch_dev; + + uartswitch_dev = device_create(sec_class, NULL, 0, NULL, "uart_switch"); + if (IS_ERR(uartswitch_dev)) { + pr_err("Failed to create device(uart_switch)!\n"); + return; + } + + ret = gpio_request(GPIO_UART_SEL, "UART_SEL"); + if (ret < 0) { + pr_err("Failed to request GPIO_UART_SEL!\n"); + return; + } + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); +// gpio_direction_output(GPIO_UART_SEL, 1); + + gpio_export(GPIO_UART_SEL, 1); + + gpio_export_link(uartswitch_dev, "UART_SEL", GPIO_UART_SEL); +} + +static void p1_switch_init(void) +{ + sec_class = class_create(THIS_MODULE, "sec"); + + if (IS_ERR(sec_class)) + pr_err("Failed to create class(sec)!\n"); + + switch_dev = device_create(sec_class, NULL, 0, NULL, "switch"); + + if (IS_ERR(switch_dev)) + pr_err("Failed to create device(switch)!\n"); +}; + +/* << additional feature - end */ +#define SOC_DUALCAM_POWERCTRL + +/* Following are default values for UCON, ULCON and UFCON UART registers */ +#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) + +static struct s3c2410_uartcfg p1_uartcfgs[] __initdata = { + { + .hwport = 0, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, + { + .hwport = 1, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +#ifndef CONFIG_FIQ_DEBUGGER + { + .hwport = 2, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +#endif + { + .hwport = 3, + .flags = 0, + .ucon = S5PV210_UCON_DEFAULT, + .ulcon = S5PV210_ULCON_DEFAULT, + .ufcon = S5PV210_UFCON_DEFAULT, + }, +}; + +#define S5PV210_LCD_WIDTH 1024 +#define S5PV210_LCD_HEIGHT 600 + +static struct s3cfb_lcd lvds = { + .width = S5PV210_LCD_WIDTH, + .height = S5PV210_LCD_HEIGHT, + .p_width = 154, + .p_height = 90, + .bpp = 24, + .freq = 60, + + .timing = { +#if defined(CONFIG_PHONE_P1_GSM) + .h_fp = 142, //50, //179, //.h_fp = 79, + .h_bp = 210, //30, //225, //.h_bp = 200, +#elif defined(CONFIG_PHONE_P1_CDMA) + .h_fp = 100, //50, //179, //.h_fp = 79, + .h_bp = 80, //30, //225, //.h_bp = 200, +#endif + .h_sw = 50, //20, //40, + .v_fp = 10, //6, //10, + .v_fpe = 1, + .v_bp = 11, //5, //11, + .v_bpe = 1, + .v_sw = 10, // 4, //10, + }, + .polarity = { + .rise_vclk = 0, + .inv_hsync = 1, + .inv_vsync = 1, + .inv_vden = 0, + }, +}; + +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0 (12288 * SZ_1K) +// Disabled to save memory (we can't find where it's used) +//#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC1 (8192 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2 (12288 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0 (36864 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1 (36864 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD (S5PV210_LCD_WIDTH * \ + S5PV210_LCD_HEIGHT * 4 * \ + (CONFIG_FB_S3C_NR_BUFFERS + \ + (CONFIG_FB_S3C_NUM_OVLY_WIN * \ + CONFIG_FB_S3C_NUM_BUF_OVLY_WIN))) +// Was 8M, but we're only using it to encode VGA jpegs +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG (4096 * SZ_1K) +#define S5PV210_ANDROID_PMEM_MEMSIZE_PMEM (8192 * SZ_1K) +#define S5PV210_ANDROID_PMEM_MEMSIZE_PMEM_GPU1 (4200 * SZ_1K) +#define S5PV210_ANDROID_PMEM_MEMSIZE_PMEM_ADSP (1500 * SZ_1K) +#define S5PV210_VIDEO_SAMSUNG_MEMSIZE_TEXTSTREAM (4800 * SZ_1K) + +static struct s5p_media_device p1_media_devs[] = { + [0] = { + .id = S5P_MDEV_MFC, + .name = "mfc", + .bank = 0, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC0, + .paddr = 0, + }, + [1] = { + .id = S5P_MDEV_MFC, + .name = "mfc", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_MFC1, + .paddr = 0, + }, + [2] = { + .id = S5P_MDEV_FIMC0, + .name = "fimc0", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC0, + .paddr = 0, + }, +/* + [3] = { + .id = S5P_MDEV_FIMC1, + .name = "fimc1", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC1, + .paddr = 0, + }, +*/ + [4] = { + .id = S5P_MDEV_FIMC2, + .name = "fimc2", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMC2, + .paddr = 0, + }, + [5] = { + .id = S5P_MDEV_JPEG, + .name = "jpeg", + .bank = 0, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_JPEG, + .paddr = 0, + }, + [6] = { + .id = S5P_MDEV_FIMD, + .name = "fimd", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_FIMD, + .paddr = 0, + }, +#ifdef CONFIG_ANDROID_PMEM + [7] = { + .id = S5P_MDEV_PMEM, + .name = "pmem", + .bank = 0, + .memsize = S5PV210_ANDROID_PMEM_MEMSIZE_PMEM, + .paddr = 0, + }, + [8] = { + .id = S5P_MDEV_PMEM_GPU1, + .name = "pmem_gpu1", + .bank = 0, + .memsize = S5PV210_ANDROID_PMEM_MEMSIZE_PMEM_GPU1, + .paddr = 0, + }, + [9] = { + .id = S5P_MDEV_PMEM_ADSP, + .name = "pmem_adsp", + .bank = 0, + .memsize = S5PV210_ANDROID_PMEM_MEMSIZE_PMEM_ADSP, + .paddr = 0, + }, + [10] = { + .id = S5P_MDEV_TEXSTREAM, + .name = "s3c_bc", + .bank = 1, + .memsize = S5PV210_VIDEO_SAMSUNG_MEMSIZE_TEXTSTREAM, + .paddr = 0, + }, +#endif +}; + +#ifdef CONFIG_CPU_FREQ +static struct s5pv210_cpufreq_voltage smdkc110_cpufreq_volt[] = { + { + .freq = 1200000, + .varm = 1450000, + .vint = 1200000, + }, { + .freq = 1000000, + .varm = 1350000, + .vint = 1100000, + }, { + .freq = 800000, + .varm = 1275000, + .vint = 1100000, + }, { + .freq = 400000, + .varm = 1050000, + .vint = 1100000, + }, { + .freq = 200000, + .varm = 950000, + .vint = 1100000, + }, { + .freq = 100000, + .varm = 950000, + .vint = 1000000, + }, +}; + +static struct s5pv210_cpufreq_data smdkc110_cpufreq_plat = { + .volt = smdkc110_cpufreq_volt, + .size = ARRAY_SIZE(smdkc110_cpufreq_volt), +}; +#endif + +/* MAX8998 LDO */ +static struct regulator_consumer_supply ldo3_consumer[] = { + REGULATOR_SUPPLY("pd_io", "s3c-usbgadget"), + { .supply = "tv", }, +}; + +static struct regulator_consumer_supply ldo4_consumer[] = { + { .supply = "v_adc", }, +}; + +static struct regulator_consumer_supply ldo7_consumer[] = { + { .supply = "vcc_vtf", }, +}; + +static struct regulator_consumer_supply ldo8_consumer[] = { + REGULATOR_SUPPLY("pd_core", "s3c-usbgadget"), + { .supply = "tvout", }, +}; + +static struct regulator_consumer_supply ldo11_consumer[] = { + { .supply = "cam_io", }, +}; + +static struct regulator_consumer_supply ldo12_consumer[] = { + { .supply = "cam_cif", }, +}; + +static struct regulator_consumer_supply ldo13_consumer[] = { + { .supply = "cam_analog", }, +}; + +static struct regulator_consumer_supply ldo14_consumer[] = { + { .supply = "cam_3m", }, +}; + +static struct regulator_consumer_supply ldo15_consumer[] = { + { .supply = "cam_af", }, +}; + +static struct regulator_consumer_supply ldo16_consumer[] = { + { .supply = "vcc_motor", }, +}; + +static struct regulator_consumer_supply ldo17_consumer[] = { + { .supply = "vcc_lcd", }, +}; + +static struct regulator_consumer_supply buck1_consumer[] = { + { .supply = "vddarm", }, +}; + +static struct regulator_consumer_supply buck2_consumer[] = { + { .supply = "vddint", }, +}; + +static struct regulator_consumer_supply buck3_consumer[] = { + { .supply = "vcc_ram", }, +}; + +static struct regulator_consumer_supply safeout1_consumer[] = { + { .supply = "vbus_ap", }, +}; + +static struct regulator_consumer_supply safeout2_consumer[] = { + { .supply = "vbus_cp", }, +}; + +static struct regulator_init_data p1_ldo2_data = { + .constraints = { + .name = "VALIVE_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data p1_ldo3_data = { + .constraints = { + .name = "VUSB_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), + .consumer_supplies = ldo3_consumer, +}; + +static struct regulator_init_data p1_ldo4_data = { + .constraints = { + .name = "VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 3300000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo4_consumer), + .consumer_supplies = ldo4_consumer, +}; + +static struct regulator_init_data p1_ldo7_data = { + .constraints = { + .name = "VTF_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), + .consumer_supplies = ldo7_consumer, +}; + +static struct regulator_init_data p1_ldo8_data = { + .constraints = { + .name = "VUSB_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), + .consumer_supplies = ldo8_consumer, +}; + +static struct regulator_init_data p1_ldo9_data = { + .constraints = { + .name = "VCC_2.8V_PDA", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data p1_ldo11_data = { + .constraints = { + .name = "CAM_IO_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), + .consumer_supplies = ldo11_consumer, +}; + +static struct regulator_init_data p1_ldo12_data = { + .constraints = { + .name = "CAM_CIF_1.5V", + .min_uV = 1500000, + .max_uV = 1500000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo12_consumer), + .consumer_supplies = ldo12_consumer, +}; + +static struct regulator_init_data p1_ldo13_data = { + .constraints = { + .name = "CAM_A_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo13_consumer), + .consumer_supplies = ldo13_consumer, +}; + +static struct regulator_init_data p1_ldo14_data = { + .constraints = { + .name = "CAM_3M_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), + .consumer_supplies = ldo14_consumer, +}; + +static struct regulator_init_data p1_ldo15_data = { + .constraints = { + .name = "CAM_AF_3.0V", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo15_consumer), + .consumer_supplies = ldo15_consumer, +}; + +static struct regulator_init_data p1_ldo16_data = { + .constraints = { + .name = "MOTOR_3.4V", + .min_uV = 3400000, + .max_uV = 3400000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 3400000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo16_consumer), + .consumer_supplies = ldo16_consumer, +}; + +static struct regulator_init_data p1_ldo17_data = { + .constraints = { + .name = "LVDS_VDD3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 3300000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), + .consumer_supplies = ldo17_consumer, +}; + +static struct regulator_init_data p1_buck1_data = { + .constraints = { + .name = "VDD_ARM", + .min_uV = 750000, + .max_uV = 1500000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1250000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), + .consumer_supplies = buck1_consumer, +}; + + +static struct regulator_init_data p1_buck2_data = { + .constraints = { + .name = "VDD_INT", + .min_uV = 750000, + .max_uV = 1500000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1100000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), + .consumer_supplies = buck2_consumer, +}; + +static struct regulator_init_data p1_buck3_data = { + .constraints = { + .name = "VCC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .boot_on = 1, + .always_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .uV = 1800000, + .mode = REGULATOR_MODE_NORMAL, + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck3_consumer), + .consumer_supplies = buck3_consumer, +}; + +static struct regulator_init_data p1_safeout1_data = { + .constraints = { + .name = "USB_VBUS_AP", + .min_uV = 5000000, + .max_uV = 5000000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(safeout1_consumer), + .consumer_supplies = safeout1_consumer, +}; + +static struct regulator_init_data p1_safeout2_data = { + .constraints = { + .name = "USB_VBUS_CP", + .min_uV = 5000000, + .max_uV = 5000000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(safeout2_consumer), + .consumer_supplies = safeout2_consumer, +}; + +static struct max8998_regulator_data p1_regulators[] = { + { MAX8998_LDO2, &p1_ldo2_data }, + { MAX8998_LDO3, &p1_ldo3_data }, + { MAX8998_LDO4, &p1_ldo4_data }, + { MAX8998_LDO7, &p1_ldo7_data }, + { MAX8998_LDO8, &p1_ldo8_data }, + { MAX8998_LDO9, &p1_ldo9_data }, + { MAX8998_LDO11, &p1_ldo11_data }, + { MAX8998_LDO12, &p1_ldo12_data }, + { MAX8998_LDO13, &p1_ldo13_data }, + { MAX8998_LDO14, &p1_ldo14_data }, + { MAX8998_LDO15, &p1_ldo15_data }, + { MAX8998_LDO16, &p1_ldo16_data }, + { MAX8998_LDO17, &p1_ldo17_data }, + { MAX8998_BUCK1, &p1_buck1_data }, + { MAX8998_BUCK2, &p1_buck2_data }, + { MAX8998_BUCK3, &p1_buck3_data }, + { MAX8998_ESAFEOUT1, &p1_safeout1_data }, + { MAX8998_ESAFEOUT2, &p1_safeout2_data }, +}; + +static struct sec_battery_adc_table_data temper_table[] = { + /* ADC, Temperature (C/10) */ + { 1830, -200}, + { 1819, -190}, + { 1809, -180}, + { 1798, -170}, + { 1788, -160}, + { 1778, -150}, + { 1767, -140}, + { 1756, -130}, + { 1745, -120}, + { 1734, -110}, + { 1723, -100}, + { 1710, -90 }, + { 1697, -80 }, + { 1685, -70 }, + { 1672, -60 }, + { 1660, -50 }, + { 1638, -40 }, + { 1616, -30 }, + { 1594, -20 }, + { 1572, -10 }, + { 1550, 0 }, + { 1532, 10 }, + { 1514, 20 }, + { 1494, 30 }, + { 1478, 40 }, + { 1461, 50 }, + { 1437, 60 }, + { 1414, 70 }, + { 1390, 80 }, + { 1367, 90 }, + { 1344, 100 }, + { 1322, 110 }, + { 1300, 120 }, + { 1279, 130 }, + { 1257, 140 }, + { 1236, 150 }, + { 1208, 160 }, + { 1181, 170 }, + { 1153, 180 }, + { 1126, 190 }, + { 1099, 200 }, + { 1076, 210 }, + { 1054, 220 }, + { 1031, 230 }, + { 1009, 240 }, + { 987, 250 }, + { 965, 260 }, + { 943, 270 }, + { 921, 280 }, + { 899, 290 }, + { 877, 300 }, + { 852, 310 }, + { 828, 320 }, + { 803, 330 }, + { 779, 340 }, + { 755, 350 }, + { 734, 360 }, + { 713, 370 }, + { 693, 380 }, + { 672, 390 }, + { 652, 400 }, + { 634, 410 }, + { 617, 420 }, + { 600, 430 }, + { 583, 440 }, + { 566, 450 }, + { 547, 460 }, + { 528, 470 }, + { 509, 480 }, + { 490, 490 }, + { 471, 500 }, + { 457, 510 }, + { 443, 520 }, + { 429, 530 }, + { 415, 540 }, + { 402, 550 }, + { 389, 560 }, + { 376, 570 }, + { 364, 580 }, + { 351, 590 }, + { 339, 600 }, + { 328, 610 }, + { 317, 620 }, + { 306, 630 }, + { 295, 640 }, + { 284, 650 }, + { 273, 660 }, + { 263, 670 }, + { 252, 680 }, + { 242, 690 }, + { 232, 700 }, +}; + + +static void sec_battery_register_callbacks( + struct sec_battery_callbacks *ptr) +{ + callbacks = ptr; + /* if there was a cable status change before the charger was + ready, send this now */ + if ((set_cable_status != 0) && callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); + + if ((charging_status != 0) && callbacks && callbacks->set_status) + callbacks->set_status(callbacks, charging_status); +} + +static int max17042_callbacks(int request_mode, int arg1, int arg2) +{ + int ret = 0; + + if(!max17042_cb) { + printk("%s: callbacks are not registerd!!\n", __func__); + return -1; + } + + //printk("%s: request_mode(%d), arg1(%d), arg2(%d)\n", __func__, request_mode, arg1, arg2); + + switch(request_mode) { + case REQ_FULL_CHARGE_COMPENSATION: + if(max17042_cb->full_charge_comp) + max17042_cb->full_charge_comp(max17042_cb, arg1, arg2); + break; + + case REQ_VF_FULLCAP_RANGE_CHECK: + if(max17042_cb->vf_fullcap_check) + max17042_cb->vf_fullcap_check(max17042_cb); + break; + + case REQ_CAP_CORRUPTION_CHECK: + if(max17042_cb->corruption_check) + ret = max17042_cb->corruption_check(max17042_cb); + break; + + case REQ_LOW_BATTERY_COMPENSATION: + if(max17042_cb->low_batt_comp) + max17042_cb->low_batt_comp(max17042_cb, arg1); + break; + + case REQ_ADJUST_CAPACITY_RESTART: + if(max17042_cb->adjust_capacity) + ret = max17042_cb->adjust_capacity(max17042_cb); + break; + + case REQ_TEST_MODE_INTERFACE: + if(max17042_cb->test_mode_request) + ret = max17042_cb->test_mode_request(max17042_cb, + (max17042_test_mode_type_t)arg1, arg2); + break; + + default: + break; + } + + return ret; + +} + +static bool sec_battery_get_jig_status(void) +{ + return fsa9480_jig_status; +} + +static struct sec_battery_platform_data sec_battery_pdata = { + .register_callbacks = &sec_battery_register_callbacks, + .adc_table = temper_table, + .adc_array_size = ARRAY_SIZE(temper_table), + .fuelgauge_cb = &max17042_callbacks, + .get_jig_status = &sec_battery_get_jig_status, +}; + +struct platform_device sec_device_battery = { + .name = "sec_battery", + .id = -1, + .dev = { + .platform_data = &sec_battery_pdata, + } +}; + +static void sec_bat_set_charging_status(int status) +{ + charging_status = status; // ERROR : -1, NONE : 0, ACTIVE : 1, FULL : 2 + + if (callbacks && callbacks->set_status) + callbacks->set_status(callbacks, charging_status); +} + +static struct charger_device max8998_chgdev = { + .set_charging_status = sec_bat_set_charging_status, +}; + +static int max8998_charger_register(struct charger_device *chgdev) +{ + sec_battery_pdata.pmic_charger = chgdev; + return 0; +} + +static void max8998_charger_unregister(struct charger_device *chgdev) +{ + sec_battery_pdata.pmic_charger = NULL; +} + +static struct max8998_charger_data max8998_charger = { + .charger_dev_register = max8998_charger_register, + .charger_dev_unregister = max8998_charger_unregister, + .chgdev = &max8998_chgdev, +}; + +static struct max8998_platform_data max8998_pdata = { + .num_regulators = ARRAY_SIZE(p1_regulators), + .regulators = p1_regulators, + .charger = &max8998_charger, + .irq_base = NR_IRQS, +}; + +struct platform_device sec_device_dpram = { + .name = "dpram-device", + .id = -1, +}; + +static void lvds_cfg_gpio(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE); + } + + /* mDNIe SEL: why we shall write 0x2 ? */ +#ifndef CONFIG_FB_S3C_MDNIE + writel(0x2, S5P_MDNIE_SEL); +#else + writel(0x1, S5P_MDNIE_SEL); +#endif + + /* set drive strength to max */ +#if defined(CONFIG_PHONE_P1_GSM) + writel(0x5555557f, S5P_VA_GPIO + 0x12c); +#elif defined(CONFIG_PHONE_P1_CDMA) + writel(0x555555bf, S5P_VA_GPIO + 0x12c); +#endif + writel(0x55555555, S5P_VA_GPIO + 0x14c); + writel(0x55555555, S5P_VA_GPIO + 0x16c); + writel(0x00000055, S5P_VA_GPIO + 0x18c); + +} + +static int lvds_reset_lcd(struct platform_device *pdev) +{ + int err=0; + + return err; +} + +static int lvds_backlight_on(struct platform_device *pdev) +{ + int err=0; + + return err; +} + +static struct s3c_platform_fb lvds_data __initdata = { + .hw_ver = 0x62, + .clk_name = "sclk_fimd", //"lcd", + .nr_wins = 5, + .default_win = CONFIG_FB_S3C_DEFAULT_WINDOW, + .swap = FB_SWAP_HWORD | FB_SWAP_WORD, + + .lcd = &lvds, + .cfg_gpio = lvds_cfg_gpio, + .backlight_on = lvds_backlight_on, + .reset_lcd = lvds_reset_lcd, +}; + +#if defined(CONFIG_FB_S3C_CMC623) +static struct platform_device cmc623_pwm_backlight = { + .name = "cmc623_pwm_bl", + .id = -1, + .dev = { + .parent = &s3c_device_fb.dev, + }, +}; +#endif + +static struct platform_device sec_device_lms700 = { + .name = "lms700", + .id = -1, +}; + +void lcd_cfg_gpio_early_suspend(void) +{ + int i; + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF0(i), 0); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF1(i), 0); + } + + for (i = 0; i < 8; i++) { + s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF2(i), 0); + } + + for (i = 0; i < 4; i++) { + s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_OUTPUT); + s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE); + gpio_set_value(S5PV210_GPF3(i), 0); + } + /* drive strength to min */ + writel(0x00000000, S5P_VA_GPIO + 0x12c); /* GPF0DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x14c); /* GPF1DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x16c); /* GPF2DRV */ + writel(0x00000000, S5P_VA_GPIO + 0x18c); /* GPF3DRV */ + + /* OLED_DET */ + s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_OLED_DET, 0); + + /* LCD_RST */ + s3c_gpio_cfgpin(GPIO_MLCD_RST, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_MLCD_RST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_MLCD_RST, 0); + + /* DISPLAY_CS */ + s3c_gpio_cfgpin(GPIO_DISPLAY_CS, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_CS, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_CS, 0); + + /* DISPLAY_CLK */ + s3c_gpio_cfgpin(GPIO_DISPLAY_CLK, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_CLK, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_CLK, 0); + + /* DISPLAY_SI */ + s3c_gpio_cfgpin(GPIO_DISPLAY_SI, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DISPLAY_SI, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_DISPLAY_SI, 0); + + /* OLED_ID */ + s3c_gpio_cfgpin(GPIO_OLED_ID, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_DOWN); + + /* DIC_ID */ + s3c_gpio_cfgpin(GPIO_DIC_ID, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_DIC_ID, S3C_GPIO_PULL_DOWN); +} +EXPORT_SYMBOL(lcd_cfg_gpio_early_suspend); + +void lcd_cfg_gpio_late_resume(void) +{ + /* OLED_DET */ + s3c_gpio_cfgpin(GPIO_OLED_DET, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_OLED_DET, S3C_GPIO_PULL_NONE); + /* OLED_ID */ + s3c_gpio_cfgpin(GPIO_OLED_ID, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_OLED_ID, S3C_GPIO_PULL_NONE); + /* DIC_ID */ + s3c_gpio_cfgpin(GPIO_DIC_ID, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_DIC_ID, S3C_GPIO_PULL_NONE); +} +EXPORT_SYMBOL(lcd_cfg_gpio_late_resume); + +#ifdef CONFIG_30PIN_CONN +struct platform_device sec_device_connector = { + .name = "acc_con", + .id = -1, +}; +#endif + +static struct i2c_gpio_platform_data i2c4_platdata = { + .sda_pin = GPIO_AP_SDA_18V, + .scl_pin = GPIO_AP_SCL_18V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c4 = { + .name = "i2c-gpio", + .id = 4, + .dev.platform_data = &i2c4_platdata, +}; + +static struct i2c_gpio_platform_data i2c5_platdata = { + .sda_pin = GPIO_AP_SDA_28V, + .scl_pin = GPIO_AP_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c5 = { + .name = "i2c-gpio", + .id = 5, + .dev.platform_data = &i2c5_platdata, +}; + +static struct i2c_gpio_platform_data i2c6_platdata = { + .sda_pin = GPIO_AP_PMIC_SDA, + .scl_pin = GPIO_AP_PMIC_SCL, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c6 = { + .name = "i2c-gpio", + .id = 6, + .dev.platform_data = &i2c6_platdata, +}; + +static struct i2c_gpio_platform_data i2c7_platdata = { + .sda_pin = GPIO_USB_SW_SDA, + .scl_pin = GPIO_USB_SW_SCL, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c7 = { + .name = "i2c-gpio", + .id = 7, + .dev.platform_data = &i2c7_platdata, +}; + +static struct i2c_gpio_platform_data i2c8_platdata = { + .sda_pin = GYRO_SDA_28V, + .scl_pin = GYRO_SCL_28V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c8 = { + .name = "i2c-gpio", + .id = 8, + .dev.platform_data = &i2c8_platdata, +}; + + +static struct i2c_gpio_platform_data i2c9_platdata = { + .sda_pin = GPIO_FUEL_AP_SDA, + .scl_pin = GPIO_FUEL_AP_SCL, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c9 = { + .name = "i2c-gpio", + .id = 9, + .dev.platform_data = &i2c9_platdata, +}; + +static struct i2c_gpio_platform_data i2c10_platdata = { + .sda_pin = GPIO_AP_SDA_2_8V, + .scl_pin = GPIO_AP_SCL_2_8V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c10 = { + .name = "i2c-gpio", + .id = 10, + .dev.platform_data = &i2c10_platdata, +}; + +static struct i2c_gpio_platform_data i2c11_platdata = { + .sda_pin = GPIO_CHARGER_SDA_2_8V, + .scl_pin = GPIO_CHARGER_SCL_2_8V, + .udelay = 2, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c11 = { + .name = "i2c-gpio", + .id = 11, + .dev.platform_data = &i2c11_platdata, +}; + +#if defined(CONFIG_FB_S3C_CMC623) +static struct platform_device sec_device_tune_cmc623 = { // P1_LSJ : DE06 + .name = "sec_tune_cmc623", + .id = -1, +}; +#endif + +static struct i2c_gpio_platform_data i2c13_platdata = { + .sda_pin = GPIO_CMC_SDA_18V, + .scl_pin = GPIO_CMC_SCL_18V, + .udelay = 1, /* 500KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c13 = { + .name = "i2c-gpio", + .id = 13, + .dev.platform_data = &i2c13_platdata, +}; + +#if defined (CONFIG_VIDEO_NM6XX) +static struct i2c_gpio_platform_data i2c15_platdata = { + .sda_pin = GPIO_ISDBT_SDA, + .scl_pin = GPIO_ISDBT_SCL, + .udelay = 2/*5*/, /* 250KHz */ + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, + .scl_is_output_only = 0, +}; + +static struct platform_device p1_s3c_device_i2c15 = { + .name = "i2c-gpio", + .id = 15, + .dev.platform_data = &i2c15_platdata, +}; +#endif + +#if defined(CONFIG_KEYBOARD_GPIO) +static struct gpio_keys_button button_data[] = { + { KEY_POWER, S5PV210_GPH2(6), 1, "Power", EV_KEY, 1, 5}, + { KEY_VOLUMEUP, S5PV210_GPH3(0), 1, "Volume Up", EV_KEY, 1, 5}, + { KEY_VOLUMEDOWN, S5PV210_GPH3(1), 1, "Volume Down", EV_KEY, 1, 5}, +}; + +static struct gpio_keys_platform_data gpio_keys_data = { + .buttons = button_data, + .nbuttons = ARRAY_SIZE(button_data), + .rep = 0, +}; + +static struct platform_device gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &gpio_keys_data, + }, +}; +#else //CONFIG_KEYBOARD_GPIO +#if defined(CONFIG_INPUT_GPIO) +static struct gpio_event_direct_entry p1_keypad_key_map[] = { + { + .gpio = S5PV210_GPH2(6), + .code = KEY_POWER, + }, + { + .gpio = S5PV210_GPH3(1), + .code = KEY_VOLUMEDOWN, + }, + { + .gpio = S5PV210_GPH3(0), + .code = KEY_VOLUMEUP, + } +}; + +static struct gpio_event_input_info p1_keypad_key_info = { + .info.func = gpio_event_input_func, + .info.no_suspend = true, + .debounce_time.tv64 = 5 * NSEC_PER_MSEC, + .type = EV_KEY, + .keymap = p1_keypad_key_map, + .keymap_size = ARRAY_SIZE(p1_keypad_key_map) +}; + +static struct gpio_event_info *p1_input_info[] = { + &p1_keypad_key_info.info, +}; + + +static struct gpio_event_platform_data p1_input_data = { + .names = { + "p1-keypad", + NULL, + }, + .info = p1_input_info, + .info_count = ARRAY_SIZE(p1_input_info), +}; + +static struct platform_device p1_input_device = { + .name = GPIO_EVENT_DEV_NAME, + .id = 0, + .dev = { + .platform_data = &p1_input_data, + }, +}; +#endif //CONFIG_INPUT_GPIO +#endif + +#ifdef CONFIG_S5P_ADC +static struct s3c_adc_mach_info s3c_adc_platform __initdata = { + /* s5pc110 support 12-bit resolution */ + .delay = 10000, + .presc = 65, + .resolution = 12, +}; +#endif + +#ifdef CONFIG_VIDEO_ISX005 +static DEFINE_MUTEX(isx005_lock); +static struct regulator *cam_io_regulator; +static struct regulator *cam_a_regulator; +static struct regulator *cam_3m_regulator; +static struct regulator *cam_af_regulator; + +static bool isx005_powered_on=0; +static int isx005_regulator_init(void) +{ + if (IS_ERR_OR_NULL(cam_io_regulator)) { + cam_io_regulator = regulator_get(NULL, "cam_io"); //LDO11 + if (IS_ERR_OR_NULL(cam_io_regulator)) { + pr_err("failed to get cam_io regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_a_regulator)) { + cam_a_regulator = regulator_get(NULL, "cam_analog"); //LDO13 + if (IS_ERR_OR_NULL(cam_a_regulator)) { + pr_err("failed to get cam_a regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_3m_regulator)) { + cam_3m_regulator = regulator_get(NULL, "cam_3m"); //LDO14 + if (IS_ERR_OR_NULL(cam_3m_regulator)) { + pr_err("failed to get cam_3m regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_af_regulator)) { + cam_af_regulator = regulator_get(NULL, "cam_af"); //LDO15 + if (IS_ERR_OR_NULL(cam_af_regulator)) { + pr_err("failed to get cam_af regulator"); + return -EINVAL; + } + } + + pr_info("cam_io_regulator = %p\n", cam_io_regulator); + pr_info("cam_a_regulator = %p\n", cam_a_regulator); + pr_info("cam_3m_regulator = %p\n", cam_3m_regulator); + pr_info("cam_af_regulator = %p\n", cam_af_regulator); + + return 0; +} + +static void isx005_gpio_init(void) +{ + /* CAM_MEGA_nRST - GPJ1(5)*/ + if (gpio_request(GPIO_CAM_MEGA_nRST, "GPJ1") < 0){ + + pr_err("failed gpio_request GPJ1(GPIO_CAM_MEGA_nRST) for camera control\n"); + } + /* CAM_MEGA_EN - GPJ1(2) */ + if (gpio_request(GPIO_CAM_MEGA_EN, "GPJ1") < 0){ + + pr_err("failed gpio_request GPJ1(GPIO_CAM_MEGA_EN) for camera control(%d)\n",__LINE__); + } +} + +static int isx005_ldo_en(bool en) +{ + int err = 0; + int result; + + if (IS_ERR_OR_NULL(cam_io_regulator) || //LDO11 + IS_ERR_OR_NULL(cam_a_regulator) || //LDO13 + IS_ERR_OR_NULL(cam_3m_regulator) || //LDO14 + IS_ERR_OR_NULL(cam_af_regulator)) { //LDO15 + pr_err("Camera regulators not initialized\n"); + return -EINVAL; + } + + if (!en) + goto off; + + /* Turn CAM_3M_1.2V on */ + err = regulator_enable(cam_3m_regulator); + if (err) { + pr_err("Failed to enable regulator cam_3m_regulator\n"); + goto off; + } + udelay(50); + + /* Turn CAM_IO_2.8V on */ + err = regulator_enable(cam_io_regulator); + if (err) { + pr_err("Failed to enable regulator cam_io_regulator\n"); + goto off; + } + udelay(50); + + /* Turn CAM_A_2.8V on */ + err = regulator_enable(cam_a_regulator); + if (err) { + pr_err("Failed to enable regulator cam_a_regulator\n"); + goto off; + } + udelay(50); + + /* Turn CAM_AF_3.0V on */ + err = regulator_enable(cam_af_regulator); + if (err) { + pr_err("Failed to enable regulator cam_af_regulator\n"); + goto off; + } + + return 0; + +off: + result = err; + + err = regulator_disable(cam_a_regulator); + if (err) { + pr_err("Failed to disable regulator cam_a_regulator\n"); + result = err; + } + + err = regulator_disable(cam_af_regulator); + if (err) { + pr_err("Failed to disable regulator cam_af_regulator\n"); + result = err; + } + + err = regulator_disable(cam_io_regulator); + if (err) { + pr_err("Failed to disable regulator cam_io_regulator\n"); + result = err; + } + udelay(50); + err = regulator_disable(cam_3m_regulator); + if (err) { + pr_err("Failed to disable regulator cam_3m_regulator\n"); + result = err; + } + + return result; +} + +static int isx005_power_on(void) +{ + /* LDO on */ + int err; + + s5pv210_lock_dvfs_high_level(DVFS_LOCK_TOKEN_2, L3); + + /* can't do this earlier because regulators aren't available in + * early boot + */ + if (isx005_regulator_init()) { + pr_err("Failed to initialize camera regulators\n"); + return -EINVAL; + } + + /* CAM_MEGA_nRST - GPJ1(5)*/ + if (gpio_request(GPIO_CAM_MEGA_nRST, "GPJ1") < 0){ + + pr_err("failed gpio_request GPJ1(GPIO_CAM_MEGA_nRST) for camera control\n"); + } + + err = isx005_ldo_en(true); + if (err) + return err; + msleep(2); + + /* MCLK on - default is input, to save power when camera not on */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(GPIO_CAM_MCLK_AF)); + msleep(2); + + gpio_direction_output(GPIO_CAM_MEGA_nRST, 0); + msleep(1); + gpio_direction_output(GPIO_CAM_MEGA_nRST, 1); + msleep(1); + /* CAM_MEGA_nRST - GPJ1(5) LOW */ + gpio_set_value(GPIO_CAM_MEGA_nRST, 1); + mdelay(1); + + gpio_free(GPIO_CAM_MEGA_nRST); + return 0; +} + +static int isx005_power_off(void) +{ + int err = 0; + + s5pv210_unlock_dvfs_high_level(DVFS_LOCK_TOKEN_2); + + isx005_gpio_init(); + + /* CAM_MEGA_EN - GPJ1(2) LOW */ + gpio_direction_output(GPIO_CAM_MEGA_EN, 1); + gpio_set_value(GPIO_CAM_MEGA_EN, 0); + mdelay(3); + + + /* CAM_MEGA_nRST - GPJ1(5) LOW */ + gpio_direction_output(GPIO_CAM_MEGA_nRST, 1); + gpio_set_value(GPIO_CAM_MEGA_nRST, 0); + mdelay(1); + + /* Mclk disable - set to input function to save power */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + mdelay(1); + + err = isx005_ldo_en(false); + if (err) + return err; + mdelay(1); + + gpio_free(GPIO_CAM_MEGA_nRST); + gpio_free(GPIO_CAM_MEGA_EN); + msleep(10); + + return 0; +} + +static int isx005_power_en(int onoff) +{ + int err = 0; + mutex_lock(&isx005_lock); + /* we can be asked to turn off even if we never were turned + * on if something odd happens and we are closed + * by camera framework before we even completely opened. + */ + if (onoff != isx005_powered_on) { + if (onoff) + err = isx005_power_on(); + else{ + err = isx005_power_off(); + s3c_i2c0_force_stop(); + } + if (!err) + isx005_powered_on = onoff; + } + mutex_unlock(&isx005_lock); + + return err; +} + +int isx005_power_reset(void) +{ + isx005_power_en(0); + isx005_power_en(1); + + return 0; +} + +int isx005_cam_stdby(bool en) +{ + /* CAM_MEGA_EN - GPJ1(2) */ + if (gpio_request(GPIO_CAM_MEGA_EN, "GPJ1") < 0){ + pr_err("failed gpio_request GPJ1(GPIO_CAM_MEGA_EN) for camera control(%d)\n",__LINE__); + } + mdelay(1); + + gpio_direction_output(GPIO_CAM_MEGA_EN, 0); + msleep(1); + gpio_direction_output(GPIO_CAM_MEGA_EN, 1); + msleep(1); + + if(en) + { + gpio_set_value(GPIO_CAM_MEGA_EN, 1); + } + else + { + gpio_set_value(GPIO_CAM_MEGA_EN, 0); + } + msleep(1); + + gpio_free(GPIO_CAM_MEGA_EN); + + return 0; +} + +static struct isx005_platform_data isx005_plat = { + .default_width = 800, + .default_height = 600, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 0, +}; + +static struct i2c_board_info isx005_i2c_info = { +I2C_BOARD_INFO("ISX005", 0x1A ), + .platform_data = &isx005_plat, +}; + +static struct s3c_platform_camera isx005 = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &isx005_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 24000000, + .line_length = 1536, + .width = 800, + .height = 600, + .window = { + .left = 0, + .top = 0, + .width = 800, + .height = 600, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .initialized = 0, + .cam_power = isx005_power_en, +}; +#endif /* CONFIG_VIDEO_ISX005 */ + +#ifdef CONFIG_VIDEO_NM6XX + +static int nm6xx_power_en(int onoff) +{ + printk("============== NM6XX Tuner Sensor ============== \n"); + + return 0; +} + +static struct nm6xx_platform_data nm6xx_plat = { + .default_width = 320, + .default_height = 240, + .pixelformat = V4L2_PIX_FMT_YUYV, + .freq = 13500000, + .is_mipi = 0, +}; + +static struct i2c_board_info nm6xx_i2c_info = { +// I2C_BOARD_INFO("ISX005", 0x78 >> 1), +// I2C_BOARD_INFO("ISX005", 0x1A >> 1), + I2C_BOARD_INFO("NM6XX", 0x1A ), + .platform_data = &nm6xx_plat, +}; + +static struct s3c_platform_camera nm6xx = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT,//ITU_656_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_YCBYCR,//CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &nm6xx_i2c_info, + .pixelformat = V4L2_PIX_FMT_YUYV, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 6750000, + .line_length = 320, + .width = 320, + .height = 240, + .window = { + .left = 0, + .top = 0, + .width = 320, + .height = 240, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .initialized = 0, + .cam_power = nm6xx_power_en, +}; + +static struct s3c_platform_camera dummy = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT,//ITU_656_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_YCBYCR,//CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = NULL, + .pixelformat = V4L2_PIX_FMT_YUYV, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 6750000, + .line_length = 320, + .width = 320, + .height = 240, + .window = { + .left = 0, + .top = 0, + .width = 320, + .height = 240, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .initialized = 0, + .cam_power = NULL, +}; +#endif + +#ifdef CONFIG_VIDEO_S5K6AAFX +/* External camera module setting */ +static DEFINE_MUTEX(s5k6aafx_lock); +static struct regulator *cam_io_regulator; +static struct regulator *cam_a_regulator; +static struct regulator *cam_cif_regulator; +static bool s5k6aafx_powered_on=0; +static int s5k6aafx_regulator_init(void) +{ + if (IS_ERR_OR_NULL(cam_io_regulator)) { + cam_io_regulator = regulator_get(NULL, "cam_io"); //LDO11 + if (IS_ERR_OR_NULL(cam_io_regulator)) { + pr_err("failed to get cam_io regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_cif_regulator)) { + cam_cif_regulator = regulator_get(NULL, "cam_cif"); //LDO12 + if (IS_ERR_OR_NULL(cam_cif_regulator)) { + pr_err("failed to get cam_cif regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_a_regulator)) { + cam_a_regulator = regulator_get(NULL, "cam_analog"); //LDO13 + if (IS_ERR_OR_NULL(cam_a_regulator)) { + pr_err("failed to get cam_a regulator"); + return -EINVAL; + } + } + + pr_info("cam_io_regulator = %p\n", cam_io_regulator); + pr_info("cam_cif_regulator = %p\n", cam_cif_regulator); + pr_info("cam_a_regulator = %p\n", cam_a_regulator); + + return 0; +} + +static void s5k6aafx_gpio_init(void) +{ + int err; + + /* CAM_VGA_nSTBY - GPB(0) */ + err = gpio_request(GPIO_CAM_VGA_nSTBY, "GPB0"); + if (err) { + pr_err("Failed to request GPB0(GPIO_CAM_VGA_nSTBY) for camera control\n"); + } + /* CAM_VGA_nRST - GPB(2) */ + err = gpio_request(GPIO_CAM_VGA_nRST, "GPB2"); + if (err) { + pr_err("Failed to request GPB2(GPIO_CAM_VGA_nRST) for camera control\n"); + } +} + +static int s5k6aafx_ldo_en(bool en) +{ + int err = 0; + int result; + + if (IS_ERR_OR_NULL(cam_io_regulator) || //LDO11 + IS_ERR_OR_NULL(cam_cif_regulator) || //LDO12 + IS_ERR_OR_NULL(cam_a_regulator)){ //LDO13 + pr_err("Camera regulators not initialized\n"); + return -EINVAL; + } + + if (!en) + goto off; + + /* Turn CAM_A_2.8V on */ + err = regulator_enable(cam_io_regulator); + if (err) { + pr_err("Failed to enable regulator cam_io_regulator\n"); + goto off; + } + udelay(50); + + /* Turn CAM_CIF_1.8V on */ + err = regulator_enable(cam_cif_regulator); + if (err) { + pr_err("Failed to enable regulator cam_cif_regulator\n"); + goto off; + } + udelay(50); + + /* Turn CAM_A_2.8V on */ + err = regulator_enable(cam_a_regulator); + if (err) { + pr_err("Failed to enable regulator cam_a_regulator\n"); + goto off; + } + udelay(50); + + return 0; + +off: + result = err; + + err = regulator_disable(cam_io_regulator); + if (err) { + pr_err("Failed to disable regulator cam_io_regulator\n"); + result = err; + } + udelay(50); + + err = regulator_disable(cam_cif_regulator); + if (err) { + pr_err("Failed to disable regulator cam_cif_regulator\n"); + result = err; + } + udelay(50); + + err = regulator_disable(cam_a_regulator); + if (err) { + pr_err("Failed to disable regulator cam_a_regulator\n"); + result = err; + } + udelay(50); + + return result; + +} + + +static int s5k6aafx_power_on(void) +{ + /* LDO on */ + int err = 0; + + s5pv210_lock_dvfs_high_level(DVFS_LOCK_TOKEN_2, L3); + + /* can't do this earlier because regulators aren't available in + * early boot + */ + if (s5k6aafx_regulator_init()) { + pr_err("Failed to initialize camera regulators\n"); + return -EINVAL; + } + + s5k6aafx_gpio_init(); + + err = s5k6aafx_ldo_en(true); + if (err) + return err; + + /* CAM_VGA_nSTBY HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 1); + udelay(500); + + /* MCLK on - default is input, to save power when camera not on */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(GPIO_CAM_MCLK_AF)); + udelay(200); + + /* CAM_VGA_nRST HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 0); + gpio_set_value(GPIO_CAM_VGA_nRST, 1); + udelay(500); + + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_CAM_VGA_nRST); + + return 0; +} + +static int s5k6aafx_power_off(void) +{ + int err = 0; + + s5pv210_unlock_dvfs_high_level(DVFS_LOCK_TOKEN_2); + + s5k6aafx_gpio_init(); + + /* CAM_VGA_nRST LOW */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 1); + gpio_set_value(GPIO_CAM_VGA_nRST, 0); + udelay(200); + + /* Mclk disable - set to input function to save power */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + udelay(50); + + /* CAM_VGA_nSTBY LOW */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + udelay(500); + + err = s5k6aafx_ldo_en(false); + if (err) + return err; + + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_CAM_VGA_nRST); + + return 0; +} + +static int s5k6aafx_power_en(int onoff) +{ + int err = 0; + mutex_lock(&s5k6aafx_lock); + /* we can be asked to turn off even if we never were turned + * on if something odd happens and we are closed + * by camera framework before we even completely opened. + */ + if (onoff != s5k6aafx_powered_on) { + if (onoff) + err = s5k6aafx_power_on(); + else{ + err = s5k6aafx_power_off(); + s3c_i2c0_force_stop(); + } + if (!err) + s5k6aafx_powered_on = onoff; + } + mutex_unlock(&s5k6aafx_lock); + return err; +} + +int s5k6aafx_power_reset(void) +{ + s5k6aafx_power_en(0); + s5k6aafx_power_en(1); + + return 0; +} + +static struct s5k6aafx_platform_data s5k6aafx_plat = { + .default_width = 800, + .default_height = 600, + .pixelformat = V4L2_PIX_FMT_UYVY, +}; + +static struct i2c_board_info s5k6aafx_i2c_info = { + I2C_BOARD_INFO("S5K6AAFX", 0x78 >> 1), + .platform_data = &s5k6aafx_plat, +}; + +static struct s3c_platform_camera s5k6aafx = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_YCBYCR, + .i2c_busnum = 0, + .info = &s5k6aafx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 24000000, + .line_length = 800, + .width = 800, + .height = 600, + .window = { + .left = 0, + .top = 0, + .width = 800, + .height = 600, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + + .initialized = 0, + .cam_power = s5k6aafx_power_en, +}; +#endif //CONFIG_VIDEO_S5K6AAFX + +#ifdef CONFIG_VIDEO_S5K5CCGX +static DEFINE_MUTEX(s5k5ccgx_lock); +/*static struct regulator *s5k5ccgx_cam_io_regulator; +static struct regulator *s5k5ccgx_cam_a_regulator; +static struct regulator *s5k5ccgx_cam_3m_regulator; +static struct regulator *s5k5ccgx_cam_af_regulator;*/ + +static bool s5k5ccgx_powered_on=0; +static int s5k5ccgx_regulator_init(void) +{ + if (IS_ERR_OR_NULL(cam_io_regulator)) { + cam_io_regulator = regulator_get(NULL, "cam_io"); //LDO11 + if (IS_ERR_OR_NULL(cam_io_regulator)) { + pr_err("failed to get cam_io regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_a_regulator)) { + cam_a_regulator = regulator_get(NULL, "cam_analog"); //LDO13 + if (IS_ERR_OR_NULL(cam_a_regulator)) { + pr_err("failed to get cam_a regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_3m_regulator)) { + cam_3m_regulator = regulator_get(NULL, "cam_3m"); //LDO14 + if (IS_ERR_OR_NULL(cam_3m_regulator)) { + pr_err("failed to get cam_3m regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_af_regulator)) { + cam_af_regulator = regulator_get(NULL, "cam_af"); //LDO15 + if (IS_ERR_OR_NULL(cam_af_regulator)) { + pr_err("failed to get cam_af regulator"); + return -EINVAL; + } + } + if (IS_ERR_OR_NULL(cam_cif_regulator)) { + cam_cif_regulator = regulator_get(NULL, "cam_cif"); //LDO12 + if (IS_ERR_OR_NULL(cam_cif_regulator)) { + pr_err("failed to get cam_cif regulator"); + return -EINVAL; + } + } + + pr_info("cam_io_regulator = %p\n", cam_io_regulator); + pr_info("cam_a_regulator = %p\n", cam_a_regulator); + pr_info("cam_3m_regulator = %p\n", cam_3m_regulator); + pr_info("cam_af_regulator = %p\n", cam_af_regulator); + pr_info("cam_cif_regulator = %p\n", cam_cif_regulator); + return 0; +} + +static void s5k5ccgx_gpio_init(void) +{ + // CAM_MEGA_nRST - GPJ1(5) + if (gpio_request(GPIO_CAM_MEGA_nRST, "GPJ1") < 0){ + pr_err("failed gpio_request GPJ1(GPIO_CAM_MEGA_nRST) for camera control\n"); + } + // CAM_MEGA_EN - GPJ1(2) + if (gpio_request(GPIO_CAM_MEGA_EN, "GPJ1") < 0){ + pr_err("failed gpio_request GPJ1(GPIO_CAM_MEGA_EN) for camera control(%d)\n",__LINE__); + } +#ifdef SOC_DUALCAM_POWERCTRL + // CAM_VGA_nSTBY - GPB(0)/ + if(gpio_request(GPIO_CAM_VGA_nSTBY, "GPB0") < 0){ + pr_err("Failed to request GPB0(GPIO_CAM_VGA_nSTBY) for camera control\n"); + } + // CAM_VGA_nRST - GPB(2) + if(gpio_request(GPIO_CAM_VGA_nRST, "GPB2") < 0){ + pr_err("Failed to request GPB2(GPIO_CAM_VGA_nRST) for camera control\n"); + } +#endif +} + +static int s5k5ccgx_ldo_en(bool en) +{ + int err = 0; + int result; + + if (IS_ERR_OR_NULL(cam_io_regulator) || //LDO11 + IS_ERR_OR_NULL(cam_cif_regulator) || //LDO12 + IS_ERR_OR_NULL(cam_a_regulator) || //LDO13 + IS_ERR_OR_NULL(cam_3m_regulator) || //LDO14 + IS_ERR_OR_NULL(cam_af_regulator)) { //LDO15 + pr_err("Camera regulators not initialized\n"); + return -EINVAL; + } + + if (!en) + goto off; + + /* Turn CAM_A_2.8V on */ + err = regulator_enable(cam_a_regulator); + if (err) { + pr_err("Failed to enable regulator s5k5ccgx_cam_a_regulator\n"); + goto off; + } + +#ifdef SOC_DUALCAM_POWERCTRL + /* Turn CAM_CIF_1.8V on */ + err = regulator_enable(cam_cif_regulator); + if (err) { + pr_err("Failed to enable regulator cam_cif_regulator\n"); + goto off; + } + udelay(50); +#endif + + /* Turn CAM_3M_1.2V on */ + err = regulator_enable(cam_3m_regulator); + if (err) { + pr_err("Failed to enable regulator s5k5ccgx_cam_3m_regulator\n"); + goto off; + } + + /* Turn CAM_AF_3.0V on */ + err = regulator_enable(cam_af_regulator); + if (err) { + pr_err("Failed to enable regulator s5k5ccgx_cam_af_regulator\n"); + goto off; + } + + /* Turn CAM_IO_2.8V on */ + err = regulator_enable(cam_io_regulator); + if (err) { + pr_err("Failed to enable regulator s5k5ccgx_cam_io_regulator\n"); + goto off; + } + + return 0; + +off: + result = err; + + err = regulator_disable(cam_io_regulator); + if (err) { + pr_err("Failed to disable regulator s5k5ccgx_cam_io_regulator\n"); + result = err; + } + + err = regulator_disable(cam_af_regulator); + if (err) { + pr_err("Failed to disable regulator s5k5ccgx_cam_af_regulator\n"); + result = err; + } + + err = regulator_disable(cam_3m_regulator); + if (err) { + pr_err("Failed to disable regulator s5k5ccgx_cam_3m_regulator\n"); + result = err; + } + + err = regulator_disable(cam_a_regulator); + if (err) { + pr_err("Failed to disable regulator s5k5ccgx_cam_a_regulator\n"); + result = err; + } + + return result; +} + +static int s5k5ccgx_power_on(void) +{ + /* LDO on */ + int err; + + s5pv210_lock_dvfs_high_level(DVFS_LOCK_TOKEN_2, L3); + + /* can't do this earlier because regulators aren't available in + * early boot + */ + if (s5k5ccgx_regulator_init()) { + pr_err("Failed to initialize camera regulators\n"); + return -EINVAL; + } + + s5k5ccgx_gpio_init(); + + err = s5k5ccgx_ldo_en(true); + if (err){ + return err; + } + +#ifdef SOC_DUALCAM_POWERCTRL + udelay(60); + /* CAM_VGA_nSTBY HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 0); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 1); + mdelay(5); +#endif + /* MCLK on - default is input, to save power when camera not on */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, S3C_GPIO_SFN(GPIO_CAM_MCLK_AF)); + +#ifdef SOC_DUALCAM_POWERCTRL + /* CAM_VGA_nRST HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nRST, 0); + gpio_set_value(GPIO_CAM_VGA_nRST, 1); + mdelay(7); + + /* CAM_VGA_nSTBY HIGH */ + gpio_direction_output(GPIO_CAM_VGA_nSTBY, 1); + gpio_set_value(GPIO_CAM_VGA_nSTBY, 0); + udelay(20); +#endif + + /* CAM_MEGA_EN - GPJ1(2) HIGH */ + gpio_direction_output(GPIO_CAM_MEGA_EN, 0); + gpio_set_value(GPIO_CAM_MEGA_EN, 1); + mdelay(1); + + + /* CAM_MEGA_nRST - GPJ1(5) HIGH */ + gpio_direction_output(GPIO_CAM_MEGA_nRST, 0); + gpio_set_value(GPIO_CAM_MEGA_nRST, 1); + msleep(10); + + gpio_free(GPIO_CAM_MEGA_EN); + gpio_free(GPIO_CAM_MEGA_nRST); +#ifdef SOC_DUALCAM_POWERCTRL + gpio_free(GPIO_CAM_VGA_nSTBY); + gpio_free(GPIO_CAM_VGA_nRST); +#endif + + return 0; +} + +static int s5k5ccgx_power_off(void) +{ + int err = 0; + + s5pv210_unlock_dvfs_high_level(DVFS_LOCK_TOKEN_2); + + // CAM_MEGA_nRST - GPJ1(5) + if (gpio_request(GPIO_CAM_MEGA_nRST, "GPJ1") < 0){ + pr_err("failed gpio_request(GPJ1) for camera control\n"); + } + // CAM_MEGA_EN - GPJ1(2) + if (gpio_request(GPIO_CAM_MEGA_EN, "GPJ1") < 0){ + pr_err("failed gpio_request(GPJ1) for camera control\n"); + } +#ifdef SOC_DUALCAM_POWERCTRL + // CAM_VGA_nRST - GPB(2) + if(gpio_request(GPIO_CAM_VGA_nRST, "GPB2") < 0){ + pr_err("Failed to request GPB2 for camera control\n"); + } +#endif + + /* CAM_MEGA_nRST - GPJ1(5) LOW */ + gpio_direction_output(GPIO_CAM_MEGA_nRST, 1); + gpio_set_value(GPIO_CAM_MEGA_nRST, 0); + mdelay(1); + + /* Mclk disable - set to input function to save power */ + s3c_gpio_cfgpin(GPIO_CAM_MCLK, 0); + + /* CAM_MEGA_EN - GPJ1(2) LOW */ + gpio_direction_output(GPIO_CAM_MEGA_EN, 1); + gpio_set_value(GPIO_CAM_MEGA_EN, 0); + +#ifdef SOC_DUALCAM_POWERCTRL + gpio_direction_output(GPIO_CAM_VGA_nRST, 1); + gpio_set_value(GPIO_CAM_VGA_nRST, 0); +#endif + + err = s5k5ccgx_ldo_en(false); + if (err) + { + return err; + } + + gpio_free(GPIO_CAM_MEGA_EN); + gpio_free(GPIO_CAM_MEGA_nRST); +#ifdef SOC_DUALCAM_POWERCTRL + gpio_free(GPIO_CAM_VGA_nRST); +#endif + + return 0; +} + +static int s5k5ccgx_power_en(int onoff) +{ + int err = 0; + mutex_lock(&s5k5ccgx_lock); + /* we can be asked to turn off even if we never were turned + * on if something odd happens and we are closed + * by camera framework before we even completely opened. + */ + if (onoff != s5k5ccgx_powered_on) { + if (onoff) + err = s5k5ccgx_power_on(); + else{ + err = s5k5ccgx_power_off(); + s3c_i2c0_force_stop(); + } + if (!err) + s5k5ccgx_powered_on = onoff; + } + mutex_unlock(&s5k5ccgx_lock); + return err; +} + +int s5k5ccgx_cam_stdby(bool en) +{ + printk(KERN_ERR"<MACHINE> stdby(%d)\n", en); + + mdelay(1); + + gpio_direction_output(GPIO_CAM_MEGA_EN, 0); + msleep(1); + gpio_direction_output(GPIO_CAM_MEGA_EN, 1); + msleep(1); + + if(en) + { + gpio_set_value(GPIO_CAM_MEGA_EN, 1); + } + else + { + gpio_set_value(GPIO_CAM_MEGA_EN, 0); + } + msleep(1); + + return 0; +} + +static struct s5k5ccgx_platform_data s5k5ccgx_plat = { + .default_width = 800, + .default_height = 600, + .pixelformat = V4L2_PIX_FMT_UYVY, + .freq = 24000000, + .is_mipi = 0, +}; + +static struct i2c_board_info s5k5ccgx_i2c_info = { +I2C_BOARD_INFO("S5K5CCGX", 0x78>>1 ), + .platform_data = &s5k5ccgx_plat, +}; + +static struct s3c_platform_camera s5k5ccgx = { + .id = CAMERA_PAR_A, + .type = CAM_TYPE_ITU, + .fmt = ITU_601_YCBCR422_8BIT, + .order422 = CAM_ORDER422_8BIT_CBYCRY, + .i2c_busnum = 0, + .info = &s5k5ccgx_i2c_info, + .pixelformat = V4L2_PIX_FMT_UYVY, + .srclk_name = "xusbxti", + .clk_name = "sclk_cam", + .clk_rate = 24000000, + .line_length = 1536, + .width = 800, + .height = 600, + .window = { + .left = 0, + .top = 0, + .width = 800, + .height = 600, + }, + + /* Polarity */ + .inv_pclk = 0, + .inv_vsync = 1, + .inv_href = 0, + .inv_hsync = 0, + .initialized = 0, + .cam_power = s5k5ccgx_power_en, +}; +#endif //CONFIG_VIDEO_S5K5CCGX + +/* Interface setting */ +static struct s3c_platform_fimc fimc_plat_lsi = { + .srclk_name = "mout_mpll", + .clk_name = "sclk_fimc", + .lclk_name = "fimc", + .clk_rate = 166750000, + .default_cam = CAMERA_PAR_A, + .camera = { +#ifdef CONFIG_VIDEO_ISX005 + &isx005, +#endif +#ifdef CONFIG_VIDEO_S5K6AAFX + &s5k6aafx, +#endif +#ifdef CONFIG_VIDEO_NM6XX + &dummy, + &nm6xx, +#endif + +#ifdef CONFIG_VIDEO_S5K5CCGX + &s5k5ccgx, +#endif + }, + .hw_ver = 0x43, +}; + +#ifdef CONFIG_VIDEO_JPEG_V2 +static struct s3c_platform_jpeg jpeg_plat __initdata = { + .max_main_width = 1280, + .max_main_height = 960, + .max_thumb_width = 400, + .max_thumb_height = 240, +}; +#endif + + +static struct i2c_board_info i2c_devs4[] __initdata = { + { + I2C_BOARD_INFO("wm8994-samsung", (0x34>>1)), + }, +#ifdef CONFIG_MHL_SII9234 + { + I2C_BOARD_INFO("SII9234", 0x72>>1), + }, + { + I2C_BOARD_INFO("SII9234A", 0x7A>>1), + }, + { + I2C_BOARD_INFO("SII9234B", 0x92>>1), + }, + { + I2C_BOARD_INFO("SII9234C", 0xC8>>1), + }, +#endif +}; + +static struct platform_device bma020_accel = { + .name = "bma020-accelerometer", + .id = -1, +}; + +static struct l3g4200d_platform_data l3g4200d_p1p2_platform_data = { +}; + +static struct i2c_board_info i2c_devs5[] __initdata = { + { + I2C_BOARD_INFO("bma020", 0x38), + }, + { + I2C_BOARD_INFO("l3g4200d", 0x68), + .platform_data = &l3g4200d_p1p2_platform_data, + .irq = -1, + }, +}; +/* I2C1 */ +static struct i2c_board_info i2c_devs1[] __initdata = { + { + I2C_BOARD_INFO("s5p_ddc", (0x74>>1)), + }, +}; + +/* I2C2 */ +static struct i2c_board_info i2c_devs2[] __initdata = { + { + I2C_BOARD_INFO("qt602240_ts", 0x4a), + }, +}; + + +static void l3g4200d_irq_init(void) +{ + i2c_devs5[1].irq = IRQ_EINT(29); +} + +static void fsa9480_usb_cb(bool attached) +{ + struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); + + if (gadget) { + if (attached) + usb_gadget_vbus_connect(gadget); + else { + gadget->speed = USB_SPEED_HIGH; + usb_gadget_vbus_disconnect(gadget); + } + } + + set_cable_status = attached ? CABLE_TYPE_USB : CABLE_TYPE_NONE; + + if (callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); + + if(!attached) ap_vbus_disabled = 0; // reset flag +} + +static void fsa9480_charger_cb(bool attached) +{ + set_cable_status = attached ? CABLE_TYPE_AC : CABLE_TYPE_NONE; + if (callbacks && callbacks->set_cable) + callbacks->set_cable(callbacks, set_cable_status); + + if(!attached) ap_vbus_disabled = 0; // reset flag +} + +static void fsa9480_jig_cb(bool attached) +{ + printk("%s : attached (%d)\n", __func__, (int)attached); + fsa9480_jig_status = attached; +} + +static struct switch_dev switch_dock = { + .name = "dock", +}; + +static void fsa9480_deskdock_cb(bool attached) +{ + if (attached) + switch_set_state(&switch_dock, 1); + else + switch_set_state(&switch_dock, 0); +} + +static void fsa9480_cardock_cb(bool attached) +{ + if (attached) + switch_set_state(&switch_dock, 2); + else + switch_set_state(&switch_dock, 0); +} + +static void fsa9480_reset_cb(void) +{ + int ret; + + /* for CarDock, DeskDock */ + ret = switch_dev_register(&switch_dock); + if (ret < 0) + pr_err("Failed to register dock switch. %d\n", ret); +} + +static void fsa9480_set_init_flag(void) +{ + fsa9480_init_flag = 1; +} + +static void fsa9480_usb_switch(void) +{ + // check if sec_switch init finished. + if(!sec_switch_inited) + return; + + if(sec_switch_status & (int)(USB_SEL_MASK)) { + sec_switch_set_regulator(AP_VBUS_ON); + } + else { + sec_switch_set_regulator(CP_VBUS_ON); + } +} + +static struct fsa9480_platform_data fsa9480_pdata = { + .usb_cb = fsa9480_usb_cb, + .charger_cb = fsa9480_charger_cb, + .jig_cb = fsa9480_jig_cb, + .deskdock_cb = fsa9480_deskdock_cb, + .cardock_cb = fsa9480_cardock_cb, + .reset_cb = fsa9480_reset_cb, + .set_init_flag = fsa9480_set_init_flag, + .set_usb_switch = fsa9480_usb_switch, +}; + +static struct i2c_board_info i2c_devs7[] __initdata = { + { + I2C_BOARD_INFO("fsa9480", 0x4A >> 1), + .platform_data = &fsa9480_pdata, + .irq = IRQ_EINT(23), + }, +}; + +static struct charger_device smb136_chgdev = { + .set_charging_status = sec_bat_set_charging_status, +}; + +static int smb136_charger_register(struct charger_device *chgdev) +{ + sec_battery_pdata.external_charger = chgdev; + return 0; +} + +static void smb136_charger_unregister(struct charger_device *chgdev) +{ + sec_battery_pdata.external_charger = NULL; +} + +static struct smb136_charger_data smb136_charger = { + .charger_dev_register = smb136_charger_register, + .charger_dev_unregister = smb136_charger_unregister, + .chgdev = &smb136_chgdev, +}; + +static struct i2c_board_info i2c_devs11[] __initdata = { + { + I2C_BOARD_INFO("smb136-charger", 0x9A >> 1), + .platform_data = &smb136_charger, + .irq = IRQ_EINT(9), + }, +}; + +static void __init smb136_gpio_init(void) +{ + s3c_gpio_cfgpin(GPIO_TA_nCHG, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_TA_nCHG, S3C_GPIO_PULL_NONE); +} + +static struct i2c_board_info i2c_devs6[] __initdata = { +#ifdef CONFIG_REGULATOR_MAX8998 + { + /* The address is 0xCC used since SRAD = 0 */ + I2C_BOARD_INFO("max8998", (0xCC >> 1)), + .platform_data = &max8998_pdata, + .irq = IRQ_EINT7, + }, { + I2C_BOARD_INFO("rtc_max8998", (0x0D >> 1)), + }, +#endif +}; + +static int max17042_power_supply_register(struct device *parent, + struct power_supply *psy) +{ + sec_battery_pdata.psy_fuelgauge = psy; + return 0; +} + +static void max17042_power_supply_unregister(struct power_supply *psy) +{ + sec_battery_pdata.psy_fuelgauge = NULL; +} + +static void max17042_force_status_update(void) +{ + if (callbacks && callbacks->force_update) + callbacks->force_update(callbacks); +} + +static void max17042_register_callbacks( + struct max17042_callbacks *ptr) +{ + max17042_cb = ptr; +} + +static struct max17042_platform_data max17042_pdata = { + .register_callbacks = max17042_register_callbacks, + .power_supply_register = max17042_power_supply_register, + .power_supply_unregister = max17042_power_supply_unregister, + .force_update_status = max17042_force_status_update, +}; + +static struct i2c_board_info i2c_devs9[] __initdata = { + { + I2C_BOARD_INFO("max17042", (0x6D >> 1)), + .platform_data = &max17042_pdata, + .irq = IRQ_EINT(14), + }, +}; + +static void __init max17042_gpio_init(void) +{ + s3c_gpio_cfgpin(GPIO_FUEL_ARLT, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_FUEL_ARLT, S3C_GPIO_PULL_NONE); +} + +static void ambient_light_sensor_reset(void) +{ + int gpio; + + /* BH1721FVC */ + gpio = S5PV210_GPG2(2); /* XMMC2CDn */ + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + gpio_request(gpio, "ALS_nRST"); + gpio_direction_output(gpio, 0); + + gpio_set_value(gpio, 0); + /* More than 1us */ + udelay(2); + gpio_set_value(gpio, 1); +} + +static struct bh1721_platform_data bh1721_p1p2_platform_data = { + .reset = ambient_light_sensor_reset, +}; + +static struct i2c_board_info i2c_devs10[] __initdata = { + { + I2C_BOARD_INFO("ak8973", 0x1c), + }, + { + I2C_BOARD_INFO("bh1721", 0x23), + .platform_data = &bh1721_p1p2_platform_data, + }, +}; + +static struct i2c_board_info i2c_devs13[] __initdata = { + { + I2C_BOARD_INFO("sec_tune_cmc623_i2c", 0x38), + }, +}; + +#if defined(CONFIG_VIDEO_NM6XX) + static struct i2c_board_info i2c_devs15[] __initdata = { + { + I2C_BOARD_INFO("nmi625", 0x61), + }, + }; +#endif + +static struct resource ram_console_resource[] = { + { + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ram_console_device = { + .name = "ram_console", + .id = -1, + .num_resources = ARRAY_SIZE(ram_console_resource), + .resource = ram_console_resource, +}; + +#ifdef CONFIG_ANDROID_PMEM +static struct android_pmem_platform_data pmem_pdata = { + .name = "pmem", + .no_allocator = 1, + .cached = 1, + .start = 0, + .size = 0, +}; + +static struct android_pmem_platform_data pmem_gpu1_pdata = { + .name = "pmem_gpu1", + .no_allocator = 1, + .cached = 1, + .buffered = 1, + .start = 0, + .size = 0, +}; + +static struct android_pmem_platform_data pmem_adsp_pdata = { + .name = "pmem_adsp", + .no_allocator = 1, + .cached = 1, + .buffered = 1, + .start = 0, + .size = 0, +}; + +static struct platform_device pmem_device = { + .name = "android_pmem", + .id = 0, + .dev = { .platform_data = &pmem_pdata }, +}; + +static struct platform_device pmem_gpu1_device = { + .name = "android_pmem", + .id = 1, + .dev = { .platform_data = &pmem_gpu1_pdata }, +}; + +static struct platform_device pmem_adsp_device = { + .name = "android_pmem", + .id = 2, + .dev = { .platform_data = &pmem_adsp_pdata }, +}; + +static void __init android_pmem_set_platdata(void) +{ + pmem_pdata.start = (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM, 0); + pmem_pdata.size = (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM, 0); + + pmem_gpu1_pdata.start = + (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM_GPU1, 0); + pmem_gpu1_pdata.size = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM_GPU1, 0); + + pmem_adsp_pdata.start = + (u32)s5p_get_media_memory_bank(S5P_MDEV_PMEM_ADSP, 0); + pmem_adsp_pdata.size = + (u32)s5p_get_media_memsize_bank(S5P_MDEV_PMEM_ADSP, 0); +} +#endif + + +static struct regulator *reg_safeout1; +static struct regulator *reg_safeout2; + +int sec_switch_get_regulator(void) +{ + printk("%s\n", __func__); + + // get regulators. + if (IS_ERR_OR_NULL(reg_safeout1)) { + reg_safeout1 = regulator_get(NULL, "vbus_ap"); + if (IS_ERR_OR_NULL(reg_safeout1)) { + pr_err("failed to get safeout1 regulator"); + return -1; + } + } + + if (IS_ERR_OR_NULL(reg_safeout2)) { + reg_safeout2 = regulator_get(NULL, "vbus_cp"); + if (IS_ERR_OR_NULL(reg_safeout2)) { + pr_err("failed to get safeout2 regulator"); + return -1; + } + } + +// printk("reg_safeout1 = %p\n", reg_safeout1); +// printk("reg_safeout2 = %p\n", reg_safeout2); + + return 0; +} + +int sec_switch_set_regulator(int mode) +{ + struct usb_gadget *gadget = platform_get_drvdata(&s3c_device_usbgadget); + + printk("%s (mode : %d)\n", __func__, mode); + + if (IS_ERR_OR_NULL(reg_safeout1) || + IS_ERR_OR_NULL(reg_safeout2)) { + pr_err("safeout regulators not initialized yet!!\n"); + return -EINVAL; + } + + // note : safeout1/safeout2 register setting is not matched regulator's use_count. + // so, set/reset use_count is needed to control safeout regulator correctly... + if(mode == CP_VBUS_ON) { + if(!regulator_is_enabled(reg_safeout2)) { + regulator_set_use_count(reg_safeout2, 0); + regulator_enable(reg_safeout2); + } + + if(regulator_is_enabled(reg_safeout1)) { + regulator_set_use_count(reg_safeout1, 1); + regulator_disable(reg_safeout1); + } + } + else if(mode == AP_VBUS_ON) { + /* if(!regulator_is_enabled(reg_safeout1)) */ { + regulator_set_use_count(reg_safeout1, 0); + regulator_enable(reg_safeout1); + } + + if(regulator_is_enabled(reg_safeout2)) { + regulator_set_use_count(reg_safeout2, 1); + regulator_disable(reg_safeout2); + } + } + else { // AP_VBUS_OFF + printk("%s : AP VBUS OFF\n", __func__); + + gadget->speed = USB_SPEED_UNKNOWN; + usb_gadget_vbus_disconnect(gadget); + ap_vbus_disabled = 1; // set flag + } + return 0; +} + +int sec_switch_get_cable_status(void) +{ + return (ap_vbus_disabled ? CABLE_TYPE_NONE : set_cable_status); +} + +int sec_switch_get_phy_init_status(void) +{ + return fsa9480_init_flag; +} + +void sec_switch_set_switch_status(int val) +{ + printk("%s (switch_status : %d)\n", __func__, val); + if(!sec_switch_inited) + sec_switch_inited = 1; + + sec_switch_status = val; +} + +static struct sec_switch_platform_data sec_switch_pdata = { + .get_regulator = sec_switch_get_regulator, + .set_regulator = sec_switch_set_regulator, + .get_cable_status = sec_switch_get_cable_status, + .get_phy_init_status = sec_switch_get_phy_init_status, + .set_switch_status = sec_switch_set_switch_status, +}; + +struct platform_device sec_device_switch = { + .name = "sec_switch", + .id = 1, + .dev = { + .platform_data = &sec_switch_pdata, + } +}; + +static struct platform_device sec_device_rfkill = { + .name = "bt_rfkill", + .id = -1, +}; + +static struct platform_device sec_device_btsleep = { + .name = "bt_sleep", + .id = -1, +}; + +#ifdef CONFIG_SEC_HEADSET +static struct sec_jack_port sec_jack_port_info[] = { + { + { // HEADSET detect info + .eint =IRQ_EINT8, + .gpio = GPIO_DET_35, + .gpio_af = GPIO_DET_35_AF , + .low_active = 1 + }, + { // SEND/END info + .eint = IRQ_EINT12, + .gpio = GPIO_EAR_SEND_END, + .gpio_af = GPIO_EAR_SEND_END_AF, + .low_active = 1 + } + } +}; + +static struct sec_jack_platform_data sec_jack_pdata = { + .port = sec_jack_port_info, + .nheadsets = ARRAY_SIZE(sec_jack_port_info) +}; + +static struct platform_device sec_device_jack= { + .name = "sec_jack", + .id = -1, + .dev = { + .platform_data = &sec_jack_pdata, + } +}; +#endif + + /* touch screen device init */ +static void __init qt_touch_init(void) +{ + int gpio; + + gpio = S5PV210_GPH2(1); + gpio_request(gpio, "TOUCH_EN"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT); + gpio_direction_output(gpio, 1); + + gpio = GPIO_TOUCH_INT; + gpio_request(gpio, "TOUCH_INT"); + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); +} + +#if defined (CONFIG_VIDEO_NM6XX) +static void __init nmi_i2s_cfg_gpio_init(void) +{ + s3c_gpio_cfgpin(GPIO_I2S_SCLK_18V, S3C_GPIO_SFN(0x4)); + s3c_gpio_cfgpin(GPIO_I2S_MCLK_18V, S3C_GPIO_SFN(0x4)); + s3c_gpio_cfgpin(GPIO_I2S_LRCLK_18V, S3C_GPIO_SFN(0x4)); + s3c_gpio_cfgpin(GPIO_I2S_DATA_18V, S3C_GPIO_SFN(0x4)); + + s3c_gpio_setpull(GPIO_I2S_SCLK_18V, S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(GPIO_I2S_MCLK_18V, S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(GPIO_I2S_LRCLK_18V, S3C_GPIO_PULL_NONE); + s3c_gpio_setpull(GPIO_I2S_DATA_18V, S3C_GPIO_PULL_NONE); +} +#elif defined (CONFIG_SAMSUNG_P1LN) +static void __init nmi_pwr_disable(void) +{ + int err = 0; + + if (HWREV == 13) // Disable the ISDBT PWR : Only Latin HW 0.3 + { + err = gpio_request(GPIO_ISDBT_PWR_EN, "ISDBT_EN"); + if (err) + { + printk(KERN_ERR "failed to request GPIO_ISDBT_PWR_EN for TV control\n"); + } + + gpio_request(GPIO_ISDBT_PWR_EN,"ISDBT_EN"); + udelay(50); + gpio_direction_output(GPIO_ISDBT_PWR_EN, 0); + gpio_free(GPIO_ISDBT_PWR_EN); + } +} +#endif + +#define S3C_GPIO_SETPIN_ZERO 0 +#define S3C_GPIO_SETPIN_ONE 1 +#define S3C_GPIO_SETPIN_NONE 2 + +struct gpio_init_data { + uint num; + uint cfg; + uint val; + uint pud; + uint drv; +}; + +static struct gpio_init_data p1_init_gpios[] = { + { + .num = S5PV210_GPB(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + + }, { + .num = S5PV210_GPB(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPB(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPC0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#if defined (CONFIG_SAMSUNG_P1LN) + { + .num = S5PV210_GPC1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + /*{ + .num = S5PV210_GPD0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, */ +#elif defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + /* { + .num = S5PV210_GPC1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPC1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPD0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, */ +#endif + { + .num = S5PV210_GPD0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#if defined (CONFIG_SAMSUNG_P1LN) + { + .num = S5PV210_GPD0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#elif defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) +// worked here, 2010. 11. 03 13:14 john + /*{ + .num = S5PV210_GPD0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + },*/ +#endif + { + .num = S5PV210_GPD1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPD1(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPE0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE0(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + + { + .num = S5PV210_GPE1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPE1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPF3(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPF3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG0(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + { + .num = S5PV210_GPG1(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#elif defined (CONFIG_SAMSUNG_P1LN) + { + .num = S5PV210_GPG1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#endif + { + .num = S5PV210_GPG1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG1(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG2(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPG3(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(5), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPG3(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH0(7), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, +#if defined (CONFIG_PHONE_P1_GSM) + .pud = S3C_GPIO_PULL_NONE, +#elif defined (CONFIG_PHONE_P1_CDMA) + .pud = S3C_GPIO_PULL_UP, +#endif + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH1(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(5), + .cfg = S3C_GPIO_SFN(0xF), + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH2(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPH3(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPH3(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#if defined (CONFIG_PHONE_P1_GSM) + { + .num = S5PV210_GPH3(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#elif defined (CONFIG_PHONE_P1_CDMA) + { + .num = S5PV210_GPH3(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_4X, + }, +#endif + { + .num = S5PV210_GPI(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPI(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ0(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ1(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ2(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, +// }, { +// .num = S5PV210_GPJ2(6), +// .cfg = S3C_GPIO_INPUT, +// .val = S3C_GPIO_SETPIN_NONE, +// .pud = S3C_GPIO_PULL_DOWN, +// .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ2(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ3(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(4), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(5), // TA_EN + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ3(7), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_GPJ4(0), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(1), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_GPJ4(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + { + .num = S5PV210_MP01(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#endif + { + .num = S5PV210_MP01(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + { + .num = S5PV210_MP01(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#endif + { + .num = S5PV210_MP01(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP01(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP02(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP02(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + { + .num = S5PV210_MP03(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(5), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP03(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP04(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(2), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(3), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + { + .num = S5PV210_MP04(6), + .cfg = S3C_GPIO_OUTPUT, + .val = S3C_GPIO_SETPIN_ZERO, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP04(7), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, + + { + .num = S5PV210_MP05(0), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(1), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(2), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(3), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_NONE, + .drv = S3C_GPIO_DRVSTR_1X, + }, { + .num = S5PV210_MP05(4), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + { + .num = S5PV210_MP05(6), + .cfg = S3C_GPIO_INPUT, + .val = S3C_GPIO_SETPIN_NONE, + .pud = S3C_GPIO_PULL_DOWN, + .drv = S3C_GPIO_DRVSTR_1X, + }, +#endif +}; + +void s3c_config_gpio_table(void) +{ + u32 i, gpio; + + for (i = 0; i < ARRAY_SIZE(p1_init_gpios); i++) { + gpio = p1_init_gpios[i].num; + if (gpio <= S5PV210_GPJ4(4)) { + s3c_gpio_cfgpin(gpio, p1_init_gpios[i].cfg); + s3c_gpio_setpull(gpio, p1_init_gpios[i].pud); + + if (p1_init_gpios[i].val != S3C_GPIO_SETPIN_NONE) + gpio_set_value(gpio, p1_init_gpios[i].val); + + s3c_gpio_set_drvstrength(gpio, p1_init_gpios[i].drv); + } + } +} + +#define S5PV210_PS_HOLD_CONTROL_REG (S3C_VA_SYS+0xE81C) +static void p1_power_off(void) +{ + while (1) { + /* Check reboot charging */ + if (set_cable_status) { + /* watchdog reset */ + pr_info("%s: charger connected, rebooting\n", __func__); + writel(3, S5P_INFORM6); + arch_reset('r', NULL); + pr_crit("%s: waiting for reset!\n", __func__); + while (1); + } + + /* wait for power button release */ + if (gpio_get_value(GPIO_nPOWER)) { + pr_info("%s: set PS_HOLD low\n", __func__); + + /* PS_HOLD high PS_HOLD_CONTROL, R/W, 0xE010_E81C */ + writel(readl(S5PV210_PS_HOLD_CONTROL_REG) & 0xFFFFFEFF, + S5PV210_PS_HOLD_CONTROL_REG); + + pr_crit("%s: should not reach here!\n", __func__); + } + + /* if power button is not released, wait and check TA again */ + pr_info("%s: PowerButton is not released.\n", __func__); + mdelay(1000); + } +} + +/* this table only for B4 board */ +static unsigned int p1_sleep_gpio_table[][3] = { + { S5PV210_GPA0(0), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(1), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPA1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPA1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPA1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPB(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(5), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPB(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPB(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPC0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPC1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPC1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPD0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPD1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPD1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPD1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPE0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPE1(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPE1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPE1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPF0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF0(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF1(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF2(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(4), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPF3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPF3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPG0(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_CMD + { S5PV210_GPG0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_D(0) + { S5PV210_GPG0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_D(1) + { S5PV210_GPG0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_D(2) + { S5PV210_GPG0(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_D(3) + + { S5PV210_GPG1(0), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG1(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG1(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_D(4) + { S5PV210_GPG1(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_D(5) + { S5PV210_GPG1(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_D(6) + { S5PV210_GPG1(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, // NAND_D(7) + + { S5PV210_GPG2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG2(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPG2(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPG3(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(3), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_GPG3(6), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + + /* Alive part ending and off part start*/ + { S5PV210_GPI(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPI(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ0(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ0(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ0(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ1(0), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(1), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, // GPIO_MASSMEMORY_EN + { S5PV210_GPJ1(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ1(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + { S5PV210_GPJ2(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, // GYRO_CS (NC) + { S5PV210_GPJ2(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ2(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ2(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_PHONE_P1_GSM) + { S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + { S5PV210_GPJ2(7), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif + { S5PV210_GPJ3(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(2), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(3), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ3(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ3(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_GPJ4(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_GPJ4(2), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_GPJ4(4), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + /* memory part */ + { S5PV210_MP01(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(4), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP01(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP01(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP02(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP02(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP02(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP03(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(2), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(5), S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + { S5PV210_MP03(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP03(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP04(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(1), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP04(3), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(6), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP04(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP05(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP05(5), S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + { S5PV210_MP05(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP05(7), S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + { S5PV210_MP06(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP06(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + { S5PV210_MP07(0), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(1), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(2), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(3), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(4), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(5), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(6), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + { S5PV210_MP07(7), S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + /* Memory part ending and off part ending */ +}; + + +static unsigned int p1_r04_sleep_gpio_table[][3] = { + + {S5PV210_GPA0(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(3), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPA1(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPB(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// {S5PV210_GPB(3), // GPIO_BT_nRST +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPC0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPC1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPD0(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPD1(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPE0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPE1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF3(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// This pin is controlled by sound. - GPIO_CODEC_LDO_EN + {S5PV210_GPF3(4), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPF3(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +// {S5PV210_GPG1(2), // GPIO_WLAN_nRST +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG3(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPI(0), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPI(2), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(3), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(4), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPI(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + +// {S5PV210_GPJ0(0), // GPIO_WLAN_BT_EN +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ2(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ3(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(5), // TA_EN + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ4(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// This pin is controlled by sound. - GPIO_MICBIAS_EN + {S5PV210_GPJ4(2), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPJ4(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /* memory part */ + {S5PV210_MP01(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(1), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(4), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP02(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP03(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(2), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP04(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(7), // MHL_RST + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP05(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(7), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //UART_SEL prev + + {S5PV210_MP06(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP07(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* Memory part ending and off part ending */ +}; + +static unsigned int p1_r05_sleep_gpio_table[][3] = { + + {S5PV210_GPA0(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(3), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPA1(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPB(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// {S5PV210_GPB(3), // GPIO_BT_nRST +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPC0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPC1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPD0(0), // KEY_LED_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(3), // LCD_CABC_PWM + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPD1(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPE0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPE1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF3(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// This pin is controlled by sound. - GPIO_CODEC_LDO_EN + {S5PV210_GPF3(4), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPF3(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +// {S5PV210_GPG1(2), // GPIO_WLAN_nRST +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG3(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(2), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPI(0), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPI(2), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(3), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(4), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPI(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + +// {S5PV210_GPJ0(0), // GPIO_WLAN_BT_EN +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(5), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(1), // VIBTONE_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(1), // GYRO_CS (NC) + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(4), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(5), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ3(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(5), // TA_EN + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ4(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(1), // CURR_ADJ + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +// This pin is controlled by sound. - GPIO_MICBIAS_EN + {S5PV210_GPJ4(2), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPJ4(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /* memory part */ + {S5PV210_MP01(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(4), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP02(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP03(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(2), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP04(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(7), // MHL_RST + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP05(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(7), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //UART_SEL prev + + {S5PV210_MP06(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP07(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* Memory part ending and off part ending */ +}; + +static unsigned int p1_r08_sleep_gpio_table[][3] = { + {S5PV210_GPJ1(4), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(3), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(5), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +}; + +static unsigned int p1_r09_sleep_gpio_table[][3] = { + + {S5PV210_GPA0(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(3), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPA1(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPB(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// {S5PV210_GPB(3), // GPIO_BT_nRST +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPC0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPC1(0), // CMC_SLEEP + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(1), // CMC_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(2), // CMC_RST + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(3), // CMC_SHDN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(4), // CMC_BYPASS + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPD0(0), // KEY_LED_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(3), // LCD_CABC_PWM + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPD1(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPE0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPE1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF3(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// This pin is controlled by sound. - GPIO_CODEC_LDO_EN + {S5PV210_GPF3(4), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPF3(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +// {S5PV210_GPG1(2), // GPIO_WLAN_nRST +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG3(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(2), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(3), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPI(0), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPI(2), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(3), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(4), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPI(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + +// {S5PV210_GPJ0(0), // GPIO_WLAN_BT_EN +// S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(5), // TOUCH_INT + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(1), // MESSMEMORY_EN +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPJ1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(4), // OVF_FLAG + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ2(0), // CHARGER_SDA_2.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(1), // CHARGER_SCL_2.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(2), // HDMI_EN1 + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(4), // MESSMEMORY_EN2 + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(5), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ3(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(5), // TA_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ4(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(1), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// This pin is controlled by sound. - GPIO_MICBIAS_EN + {S5PV210_GPJ4(2), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPJ4(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /* memory part */ + {S5PV210_MP01(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(4), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP02(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP03(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(2), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP04(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(3), // CMC_SCL_1.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(5), // CMC_SDA_1.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(6), // GPS_CNBTL + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(7), // MHL_RST + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP05(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(7), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, //UART_SEL prev + + {S5PV210_MP06(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP06(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP07(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP07(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + /* Memory part ending and off part ending */ +}; + +static unsigned int p1_r11_sleep_gpio_table[][3] = { + {S5PV210_GPJ1(4), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +}; + +static unsigned int p1_r12_sleep_gpio_table[][3] = { + + {S5PV210_GPA0(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(3), + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(4), +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA0(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPA1(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(2), +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPA1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPA1(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + + {S5PV210_GPB(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(1), +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPB(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_GPB(4), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(5), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(6), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPB(7), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_GPB(4), // HWREV_MODE3 + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(5), // HWREV_MODE2 + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(6), // HWREV_MODE1 + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPB(7), // HWREV_MODE0 + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPC0(0), +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_GPC1(0), // CMC_SLEEP + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(1), // CMC_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(2), // CMC_RST + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(3), // CMC_SHDN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPC1(4), // CMC_BYPASS + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_GPC1(0), // I2S_SCLK_1.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(1), // I2S_MCLK_1.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(2), // I2S_LRCLK_1.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(3), // I2S_DATA_1.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPC1(4), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPD0(0), // KEY_LED_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_GPD0(2), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_GPD0(2), // HWREV_MODE4 + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPD0(3), // LCD_CABC_PWM + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPD1(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD1(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPD1(5), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_GPE0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPE1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPE1(4), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_GPF0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF0(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF1(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF1(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(4), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF2(7), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPF3(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(1), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPF3(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// This pin is controlled by sound. - GPIO_CODEC_LDO_EN + {S5PV210_GPF3(4), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPF3(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG0(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(1), // NAND_CMD +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_GPG0(2), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_GPG0(2), // TOUCH_INT + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPG0(3), // NAND_D(0) + +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(4), // NAND_D(1) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(5), // NAND_D(2) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG0(6), // NAND_D(3) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPG1(0), // GPS_nRST + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(1), // GPS_PWR_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(4), // NAND_D(1) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(5), // NAND_D(2) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG0(6), // NAND_D(3) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_GPG1(0), // GPS_nRST + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(1), // GPS_PWR_EN + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPG1(2), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(3), // NAND_D(4) +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(4), // NAND_D(5) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(5), // NAND_D(6) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG1(6), // NAND_D(7) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(4), // NAND_D(5) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(5), // NAND_D(6) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG1(6), // NAND_D(7) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_GPG2(0), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(1), // T_FLASH_CLK + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG2(3), // T_FLASH_D(0) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(4), // T_FLASH_D(1) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(5), // T_FLASH_D(2) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPG2(6), // T_FLASH_D(3) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_GPG3(0), // WLAN_SDIO_CLK + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(1), // WLAN_SDIO_CMD + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(3), // WLAN_SDIO_D(0) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(4), // WLAN_SDIO_D(1) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(5), // WLAN_SDIO_D(2) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPG3(6), // WLAN_SDIO_D(3) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPI(0), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(2), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(3), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(4), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPI(5), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPI(6), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_GPJ0(0), // ISDBT_SCL + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(1), // ISDBT_SDA + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(2), // ISDBT_CLK + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(3), // ISDBT_SYNC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(4), // ISDBT_VALID + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(5), // ISDBT_DATA + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(6), // ISDBT_ERR + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_GPJ0(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(2), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ0(5), // TOUCH_INT + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ0(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPJ0(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_SAMSUNG_P1) + {S5PV210_GPJ1(0), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1C) + {S5PV210_GPJ1(0), // NC + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif +#if defined (CONFIG_PHONE_P1_GSM) + {S5PV210_GPJ1(1), // MESSMEMORY_EN + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + {S5PV210_GPJ1(1), // MESSMEMORY_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPJ1(2), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ1(3), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ1(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ2(0), // CHARGER_SDA_2.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(1), // CHARGER_SCL_2.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(2), // HDMI_EN1 + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(4), // BT_WAKE + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(5), // WLAN_WAKE + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ3(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(1), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, +#if defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_GPJ3(2), // ATV_RSTn (Latin Rev0.3) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_GPJ3(2), // NC(Rev0.6), CAM_LDO_EN(Rev0.7) // ATV_RSTn (Latin Rev0.3) + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_GPJ3(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(5), // TA_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(6), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(7), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + {S5PV210_GPJ4(0), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(1), // MASSMEMORY_EN2 + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +// This pin is controlled by sound. - GPIO_MICBIAS_EN + {S5PV210_GPJ4(2), + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, // audio + {S5PV210_GPJ4(3), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ4(4), + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + + /* memory part */ +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_MP01(0), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP01(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_MP01(0), // CMC_SHDN + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP01(1), // CMC_SLEEP + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP01(2), // RESET_REQ_N + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_MP01(3), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_MP01(3), // CMC_RST + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP01(4), // AP_NANDCS + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP01(5), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP01(6), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP01(7), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_MP02(0), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP02(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP02(2), // VCC_1.8V_PDA + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP02(3), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_MP03(0), // LVDS_SHDN + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(2), // NC (*) + S3C_GPIO_SLP_OUT1, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(3), // PDA_ACTIVE + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(4), // VCC_1.8V_PDA + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP03(5), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(6), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP03(7), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_MP04(0), // GPS_CNTL +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#endif + {S5PV210_MP04(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP04(2), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP04(3), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_MP04(4), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_MP04(4), // CMC_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP04(5), // CMC_SDA_1.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(6), // CMC_SCL_1.8V + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(7), // MHL_RST + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP05(0), // LCD_ID + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP05(2), // AP_SCL + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(3), // AP_SDA + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(4), // NC +#if defined (CONFIG_PHONE_P1_GSM) + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_PHONE_P1_CDMA) + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif +#if defined (CONFIG_SAMSUNG_P1) || defined (CONFIG_SAMSUNG_P1C) + {S5PV210_MP05(6), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +#elif defined (CONFIG_SAMSUNG_P1LN) + {S5PV210_MP05(6), // CMC_BYPASS + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +#endif + {S5PV210_MP05(7), //UART_SEL + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + + {S5PV210_MP06(0), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(2), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(3), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(4), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(5), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(6), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP06(7), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_MP07(0), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(1), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(2), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(3), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(4), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(5), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(6), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP07(7), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + /* Memory part ending and off part ending */ +}; + +static unsigned int p1_r15_sleep_gpio_table[][3] = { + {S5PV210_GPD0(1), // VIBTONE_PWM + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPD0(3), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_GPJ1(3), // VIBTONE_EN + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ3(2), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + + {S5PV210_MP05(0), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, + {S5PV210_MP05(1), // EAR_MICBIAS_EN + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(5), // NC + S3C_GPIO_SLP_INPUT, S3C_GPIO_PULL_DOWN}, +}; + +static unsigned int p1_r16_sleep_gpio_table[][3] = { + {S5PV210_MP04(2), // FLASH_EN1 + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP04(3), // FLASH_EN2 + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +}; + +static unsigned int p1_r18_sleep_gpio_table[][3] = { + {S5PV210_MP01(5), // EAR_MICBIAS_EN + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_NONE}, +}; + +static unsigned int p1_lcd_tft_sleep_gpio_table[][3] = { + {S5PV210_GPJ1(3), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_GPJ2(6), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, + {S5PV210_MP05(5), + S3C_GPIO_SLP_OUT0, S3C_GPIO_PULL_NONE}, +}; + +static unsigned int p1_keyboard_sleep_gpio_table[][3] = { + {S5PV210_GPJ1(4), // ACCESSORY_EN + S3C_GPIO_SLP_PREV, S3C_GPIO_PULL_UP}, +}; + +void s3c_config_sleep_gpio_table(int array_size, unsigned int (*gpio_table)[3]) +{ + u32 i, gpio; + + for (i = 0; i < array_size; i++) { + gpio = gpio_table[i][0]; + s3c_gpio_slp_cfgpin(gpio, gpio_table[i][1]); + s3c_gpio_slp_setpull_updown(gpio, gpio_table[i][2]); + } +} + +#define s3c_gpio_setpin gpio_set_value + +void s3c_config_sleep_gpio(void) +{ + // Setting the alive mode registers +#if defined (CONFIG_PHONE_P1_CDMA) + s3c_gpio_cfgpin(GPIO_AP_PS_HOLD,S3C_GPIO_INPUT); // Not used in Froyo also but confingured as similar + s3c_gpio_setpull(GPIO_AP_PS_HOLD,S3C_GPIO_PULL_DOWN); +#endif + s3c_gpio_cfgpin(GPIO_ACC_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_ACC_INT, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_BUCK_1_EN_A, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_BUCK_1_EN_A, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_BUCK_1_EN_A, 0); + + s3c_gpio_cfgpin(GPIO_BUCK_1_EN_B, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_BUCK_1_EN_B, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_BUCK_1_EN_B, 0); + + s3c_gpio_cfgpin(GPIO_BUCK_2_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_BUCK_2_EN, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_BUCK_2_EN, 0); + +#if defined(CONFIG_PHONE_P1_CDMA) + s3c_gpio_cfgpin(GPIO_ACCESSORY_INT, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_ACCESSORY_INT, S3C_GPIO_PULL_NONE); +#endif + + if(HWREV >= 0x4) { // NC + if(HWREV == 14 || HWREV == 15) { // RF_TOUCH_INT (P1000 Rev0.8, Rev0.9) + s3c_gpio_cfgpin(GPIO_GPH06, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_GPH06, S3C_GPIO_PULL_NONE); + } + else { // NC + s3c_gpio_cfgpin(GPIO_GPH06, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_GPH06, S3C_GPIO_PULL_DOWN); + } + } + + + if(HWREV < 0x4) { // NC + s3c_gpio_cfgpin(GPIO_GPH10, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_GPH10, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_GPH10, 0); + } + + + s3c_gpio_cfgpin(GPIO_MHL_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_MHL_INT, S3C_GPIO_PULL_DOWN); + + + if(HWREV < 0x4) { // NC + s3c_gpio_cfgpin(GPIO_GPH14, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_GPH14, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_GPH14, 0); + } + + s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_DOWN); + + if(HWREV >= 12) { // REMOTE_SENSE_IRQ (GT-P1000 Rev0.6) + s3c_gpio_cfgpin(GPIO_REMOTE_SENSE_IRQ, S3C_GPIO_INPUT); +#if defined(CONFIG_PHONE_P1_GSM) + s3c_gpio_setpull(GPIO_REMOTE_SENSE_IRQ, S3C_GPIO_PULL_NONE); +#elif defined(CONFIG_PHONE_P1_CDMA) + s3c_gpio_setpull(GPIO_REMOTE_SENSE_IRQ, S3C_GPIO_PULL_DOWN); +#endif + } + else { + s3c_gpio_cfgpin(GPIO_GPH20, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_GPH20, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_GPH20, 0); + } + + if(HWREV >= 12) { // TOUCH_EN (GT-P1000 Rev0.6) + s3c_gpio_cfgpin(GPIO_TOUCH_EN_REV06, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TOUCH_EN_REV06, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_TOUCH_EN_REV06, 0); + } + else { // NC + s3c_gpio_cfgpin(GPIO_GPH21, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_GPH21, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_GPH21, 0); + } + + if(HWREV >= 12) { // GYRO_INT (GT-P1000 Rev0.6) + s3c_gpio_cfgpin(GPIO_GYRO_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_GYRO_INT, S3C_GPIO_PULL_DOWN); + } + else { // NC + s3c_gpio_cfgpin(GPIO_GPH22, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_GPH22, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_GPH22, 0); + } + + if(HWREV >= 0x5) { // NC + if(HWREV == 15) { // WAKEUP_KEY(P1000 Rev0.9) + s3c_gpio_cfgpin(GPIO_GPH23, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_GPH23, S3C_GPIO_PULL_NONE); + } + else { // NC + s3c_gpio_cfgpin(GPIO_GPH23, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_GPH23, S3C_GPIO_PULL_DOWN); + } + } + else { // TOUCH_KEY_INT + s3c_gpio_cfgpin(GPIO_TOUCH_KEY_INT, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_TOUCH_KEY_INT, S3C_GPIO_PULL_NONE); + } + + s3c_gpio_cfgpin(GPIO_MSENSE_IRQ, S3C_GPIO_INPUT); +#if defined(CONFIG_PHONE_P1_GSM) + s3c_gpio_setpull(GPIO_MSENSE_IRQ, S3C_GPIO_PULL_NONE); +#elif defined(CONFIG_PHONE_P1_CDMA) + s3c_gpio_setpull(GPIO_MSENSE_IRQ, S3C_GPIO_PULL_UP); +#endif + + if(HWREV < 0x6) { // NC + s3c_gpio_cfgpin(GPIO_GPH33, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_GPH33, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_GPH33, 0); + } + + + if(HWREV < 11) { // NC + s3c_gpio_cfgpin(GPIO_GPH35, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_GPH35, S3C_GPIO_PULL_NONE); + s3c_gpio_setpin(GPIO_GPH35, 0); + } + + if(HWREV >= 0x4) { // NC + s3c_gpio_cfgpin(GPIO_GPH36, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_GPH36, S3C_GPIO_PULL_DOWN); + } + + s3c_gpio_cfgpin(GPIO_CP_RST, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_CP_RST, S3C_GPIO_PULL_UP); + + if(HWREV >= 12) { // Above P1000 Rev0.6 (1.2) + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r12_sleep_gpio_table), + p1_r12_sleep_gpio_table); + + if(HWREV >= 15) { // Above P1000 Rev0.9 + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r15_sleep_gpio_table), + p1_r15_sleep_gpio_table); + } + + if(HWREV >= 16) { // Above P1000 Rev1.0 + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r16_sleep_gpio_table), + p1_r16_sleep_gpio_table); + } + + if(HWREV >= 18) { // Above P1000 Rev1.2 + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r18_sleep_gpio_table), + p1_r18_sleep_gpio_table); + } + if(keyboard_enable) + { + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_keyboard_sleep_gpio_table), + p1_keyboard_sleep_gpio_table); + } + } + else if(HWREV >= 8) { // Above P1000 Rev0.2 (0.8) + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r09_sleep_gpio_table), + p1_r09_sleep_gpio_table); + + if(HWREV == 11) { // Rev0.5 : only 1 gpio status is different from Rev0.3 (0.9) + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r11_sleep_gpio_table), + p1_r11_sleep_gpio_table); + } + + if(HWREV == 8) { // Rev0.2 : only 3 gpio status is different from Rev0.3 (0.9) + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r08_sleep_gpio_table), + p1_r08_sleep_gpio_table); + } + } + else if(HWREV >= 5) { // Above Rev0.5 + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r05_sleep_gpio_table), + p1_r05_sleep_gpio_table); + } + else { // Under Rev0.4 + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_r04_sleep_gpio_table), + p1_r04_sleep_gpio_table); + } + + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_lcd_tft_sleep_gpio_table), + p1_lcd_tft_sleep_gpio_table); + +#if defined (CONFIG_VIDEO_NM6XX) + if(HWREV >= 16) { + s3c_gpio_cfgpin(GPIO_ATV_RSTn_REV10, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_ATV_RSTn_REV10, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_ISDBT_PWR_EN_REV10, S3C_GPIO_INPUT); + s3c_gpio_setpull(GPIO_ISDBT_PWR_EN_REV10, S3C_GPIO_PULL_DOWN); + } + + if(HWREV == 16) { + + s3c_gpio_cfgpin(GPIO_TV_CLK_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_TV_CLK_EN, S3C_GPIO_PULL_NONE); + } +#endif +} +EXPORT_SYMBOL(s3c_config_sleep_gpio); + +static unsigned int wlan_sdio_on_table[][4] = { + {GPIO_WLAN_SDIO_CLK, GPIO_WLAN_SDIO_CLK_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_CMD, GPIO_WLAN_SDIO_CMD_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D0, GPIO_WLAN_SDIO_D0_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D1, GPIO_WLAN_SDIO_D1_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D2, GPIO_WLAN_SDIO_D2_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D3, GPIO_WLAN_SDIO_D3_AF, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, +}; + +static unsigned int wlan_sdio_off_table[][4] = { + {GPIO_WLAN_SDIO_CLK, 1, GPIO_LEVEL_LOW, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_CMD, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D0, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D1, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D2, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, + {GPIO_WLAN_SDIO_D3, 0, GPIO_LEVEL_NONE, S3C_GPIO_PULL_NONE}, +}; + +static int wlan_power_en(int onoff) +{ + if (onoff) { + s3c_gpio_cfgpin(GPIO_WLAN_HOST_WAKE, S3C_GPIO_SFN(GPIO_WLAN_HOST_WAKE_AF)); + s3c_gpio_setpull(GPIO_WLAN_HOST_WAKE, S3C_GPIO_PULL_DOWN); + + s3c_gpio_cfgpin(GPIO_WLAN_WAKE, S3C_GPIO_SFN(GPIO_WLAN_WAKE_AF)); + s3c_gpio_setpull(GPIO_WLAN_WAKE, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_WAKE, GPIO_LEVEL_LOW); + + s3c_gpio_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SFN(GPIO_WLAN_nRST_AF)); + s3c_gpio_setpull(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_nRST, GPIO_LEVEL_HIGH); + s3c_gpio_slp_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + + msleep(200); + } else { + gpio_set_value(GPIO_WLAN_nRST, GPIO_LEVEL_LOW); + s3c_gpio_slp_cfgpin(GPIO_WLAN_nRST, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_nRST, S3C_GPIO_PULL_NONE); + + if (gpio_get_value(GPIO_BT_nRST) == 0) { + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_LOW); + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + } + } + return 0; +} + +static int wlan_reset_en(int onoff) +{ + gpio_set_value(GPIO_WLAN_nRST, + onoff ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); + return 0; +} + +static int wlan_carddetect_en(int onoff) +{ + u32 i; + u32 sdio; + + if (onoff) { + for (i = 0; i < ARRAY_SIZE(wlan_sdio_on_table); i++) { + sdio = wlan_sdio_on_table[i][0]; + s3c_gpio_cfgpin(sdio, S3C_GPIO_SFN(wlan_sdio_on_table[i][1])); + s3c_gpio_setpull(sdio, wlan_sdio_on_table[i][3]); + if (wlan_sdio_on_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wlan_sdio_on_table[i][2]); + } + } else { + for (i = 0; i < ARRAY_SIZE(wlan_sdio_off_table); i++) { + sdio = wlan_sdio_off_table[i][0]; + s3c_gpio_cfgpin(sdio, S3C_GPIO_SFN(wlan_sdio_off_table[i][1])); + s3c_gpio_setpull(sdio, wlan_sdio_off_table[i][3]); + if (wlan_sdio_off_table[i][2] != GPIO_LEVEL_NONE) + gpio_set_value(sdio, wlan_sdio_off_table[i][2]); + } + } + udelay(5); + #ifdef CONFIG_S3C_DEV_HSMMC1 + sdhci_s3c_force_presence_change(&s3c_device_hsmmc1); + #else + sdhci_s3c_force_presence_change(&s3c_device_hsmmc3); + #endif + msleep(500); /* wait for carddetect */ + return 0; +} + +static struct resource wifi_resources[] = { + [0] = { + .name = "bcmdhd_wlan_irq", + .start = IRQ_EINT(20), + .end = IRQ_EINT(20), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL | IORESOURCE_IRQ_SHAREABLE, + }, +}; + +#ifdef CONFIG_DHD_USE_STATIC_BUF +static struct wifi_mem_prealloc wifi_mem_array[PREALLOC_WLAN_SEC_NUM] = { + {NULL, (WLAN_SECTION_SIZE_0 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_1 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_2 + PREALLOC_WLAN_SECTION_HEADER)}, + {NULL, (WLAN_SECTION_SIZE_3 + PREALLOC_WLAN_SECTION_HEADER)} +}; + +static void *p1_mem_prealloc(int section, unsigned long size) +{ + if (section == PREALLOC_WLAN_SEC_NUM) + return wlan_static_skb; + + if ((section < 0) || (section > PREALLOC_WLAN_SEC_NUM)) + return NULL; + + if (wifi_mem_array[section].size < size) + return NULL; + + return wifi_mem_array[section].mem_ptr; +} +#endif + +int __init p1_init_wifi_mem(void) +{ +#ifdef CONFIG_DHD_USE_STATIC_BUF + int i; + int j; + + for (i = 0 ; i < WLAN_SKB_BUF_NUM ; i++) { + wlan_static_skb[i] = dev_alloc_skb( + ((i < (WLAN_SKB_BUF_NUM / 2)) ? 4096 : 8192)); + + if (!wlan_static_skb[i]) + goto err_skb_alloc; + } + + for (i = 0 ; i < PREALLOC_WLAN_SEC_NUM ; i++) { + wifi_mem_array[i].mem_ptr = + kmalloc(wifi_mem_array[i].size, GFP_KERNEL); + + if (!wifi_mem_array[i].mem_ptr) + goto err_mem_alloc; + } + + return 0; + + err_mem_alloc: + pr_err("Failed to mem_alloc for WLAN\n"); + for (j = 0 ; j < i ; j++) + kfree(wifi_mem_array[j].mem_ptr); + + i = WLAN_SKB_BUF_NUM; + + err_skb_alloc: + pr_err("Failed to skb_alloc for WLAN\n"); + for (j = 0 ; j < i ; j++) + dev_kfree_skb(wlan_static_skb[j]); + + return -ENOMEM; +#else + return 0; +#endif +} + +/* Customized Locale table : OPTIONAL feature */ +#define WLC_CNTRY_BUF_SZ 4 +typedef struct cntry_locales_custom { + char iso_abbrev[WLC_CNTRY_BUF_SZ]; + char custom_locale[WLC_CNTRY_BUF_SZ]; + int custom_locale_rev; +} cntry_locales_custom_t; + +static cntry_locales_custom_t p1_wifi_translate_custom_table[] = { +/* Table should be filled out based on custom platform regulatory requirement */ + {"", "XY", 4}, /* universal */ + {"US", "US", 69}, /* input ISO "US" to : US regrev 69 */ + {"CA", "US", 69}, /* input ISO "CA" to : US regrev 69 */ + {"EU", "EU", 5}, /* European union countries */ + {"AT", "EU", 5}, + {"BE", "EU", 5}, + {"BG", "EU", 5}, + {"CY", "EU", 5}, + {"CZ", "EU", 5}, + {"DK", "EU", 5}, + {"EE", "EU", 5}, + {"FI", "EU", 5}, + {"FR", "EU", 5}, + {"DE", "EU", 5}, + {"GR", "EU", 5}, + {"HU", "EU", 5}, + {"IE", "EU", 5}, + {"IT", "EU", 5}, + {"LV", "EU", 5}, + {"LI", "EU", 5}, + {"LT", "EU", 5}, + {"LU", "EU", 5}, + {"MT", "EU", 5}, + {"NL", "EU", 5}, + {"PL", "EU", 5}, + {"PT", "EU", 5}, + {"RO", "EU", 5}, + {"SK", "EU", 5}, + {"SI", "EU", 5}, + {"ES", "EU", 5}, + {"SE", "EU", 5}, + {"GB", "EU", 5}, /* input ISO "GB" to : EU regrev 05 */ + {"IL", "IL", 0}, + {"CH", "CH", 0}, + {"TR", "TR", 0}, + {"NO", "NO", 0}, + {"KR", "XY", 3}, + {"AU", "XY", 3}, + {"CN", "XY", 3}, /* input ISO "CN" to : XY regrev 03 */ + {"TW", "XY", 3}, + {"AR", "XY", 3}, + {"MX", "XY", 3} +}; + +static void *p1_wifi_get_country_code(char *ccode) +{ + int size = ARRAY_SIZE(p1_wifi_translate_custom_table); + int i; + + if (!ccode) + return NULL; + + for (i = 0; i < size; i++) + if (strcmp(ccode, p1_wifi_translate_custom_table[i].iso_abbrev) == 0) + return &p1_wifi_translate_custom_table[i]; + return &p1_wifi_translate_custom_table[0]; +} + +static struct wifi_platform_data wifi_pdata = { + .set_power = wlan_power_en, + .set_reset = wlan_reset_en, + .set_carddetect = wlan_carddetect_en, +#ifdef CONFIG_DHD_USE_STATIC_BUF + .mem_prealloc = p1_mem_prealloc, +#else + .mem_prealloc = NULL, +#endif + .get_country_code = p1_wifi_get_country_code, +}; + +static struct platform_device sec_device_wifi = { + .name = "bcmdhd_wlan", + .id = 1, + .num_resources = ARRAY_SIZE(wifi_resources), + .resource = wifi_resources, + .dev = { + .platform_data = &wifi_pdata, + }, +}; + +static struct platform_device watchdog_device = { + .name = "watchdog", + .id = -1, +}; + +static struct platform_device p1_keyboard = { + .name = "p1_keyboard", + .id = -1, +}; + +static struct platform_device *p1_devices[] __initdata = { + &watchdog_device, +#ifdef CONFIG_FIQ_DEBUGGER + &s5pv210_device_fiqdbg_uart2, +#endif + &s5p_device_onenand, +#ifdef CONFIG_RTC_DRV_S3C + &s5p_device_rtc, +#endif + + &s5pv210_device_iis0, + &s3c_device_wdt, + +#ifdef CONFIG_FB_S3C + &s3c_device_fb, +#endif + + &p1_keyboard, + +#ifdef CONFIG_VIDEO_MFC50 + &s3c_device_mfc, +#endif +#ifdef CONFIG_S5P_ADC + &s3c_device_adc, +#endif +#ifdef CONFIG_VIDEO_FIMC + &s3c_device_fimc0, + &s3c_device_fimc1, + &s3c_device_fimc2, +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2 + &s3c_device_jpeg, +#endif + + &s3c_device_g3d, + &s3c_device_lcd, + +#if defined(CONFIG_SEC_HEADSET) + &sec_device_jack, +#endif + &s3c_device_i2c0, +#if defined(CONFIG_S3C_DEV_I2C1) + &s3c_device_i2c1, +#endif + +#if defined(CONFIG_S3C_DEV_I2C2) + &s3c_device_i2c2, +#endif + &p1_s3c_device_i2c4, + &p1_s3c_device_i2c5, /* accel sensor & gyro sensor*/ + &p1_s3c_device_i2c6, + &p1_s3c_device_i2c7, + &p1_s3c_device_i2c8, + &p1_s3c_device_i2c9, /* max1704x:fuel_guage */ + &p1_s3c_device_i2c11, /* smb136:charger-ic */ + &p1_s3c_device_i2c13, /*cmc623 mdnie */ +#if defined (CONFIG_VIDEO_NM6XX) + &p1_s3c_device_i2c15, /* nmi625 */ +#endif + &sec_device_switch, // samsung switch driver + +#ifdef CONFIG_USB_GADGET + &s3c_device_usbgadget, +#endif +#ifdef CONFIG_USB_ANDROID + &s3c_device_android_usb, +#ifdef CONFIG_USB_ANDROID_MASS_STORAGE + &s3c_device_usb_mass_storage, +#endif +#ifdef CONFIG_USB_ANDROID_RNDIS + &s3c_device_rndis, +#endif +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC + &s3c_device_hsmmc0, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + &s3c_device_hsmmc1, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + &s3c_device_hsmmc2, +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + &s3c_device_hsmmc3, +#endif + +#if defined(CONFIG_FB_S3C_CMC623) + &sec_device_tune_cmc623, +#endif + + &sec_device_battery, + &p1_s3c_device_i2c10, /* magnetic sensor & lightsensor */ + +#ifdef CONFIG_S5PV210_POWER_DOMAIN + &s5pv210_pd_audio, + &s5pv210_pd_cam, + &s5pv210_pd_tv, + &s5pv210_pd_lcd, + &s5pv210_pd_g3d, + &s5pv210_pd_mfc, +#endif + +#ifdef CONFIG_ANDROID_PMEM + &pmem_device, + &pmem_gpu1_device, + &pmem_adsp_device, +#endif + +#ifdef CONFIG_HAVE_PWM + &s3c_device_timer[0], + &s3c_device_timer[1], + &s3c_device_timer[2], + &s3c_device_timer[3], +#endif + +#ifdef CONFIG_CPU_FREQ + &s5pv210_device_cpufreq, +#endif + + &sec_device_rfkill, + &sec_device_btsleep, + &ram_console_device, + &sec_device_wifi, +#if defined(CONFIG_KEYBOARD_GPIO) + &gpio_keys_device, +#else +#if defined(CONFIG_INPUT_GPIO) + &p1_input_device, +#endif +#endif + +#if defined(CONFIG_VIDEO_TSI) + &s3c_device_tsi, +#endif +#if defined(CONFIG_PHONE_P1_CDMA) + //cdma modem driver + &sec_device_dpram, +#endif + &samsung_asoc_dma, +}; + +unsigned int HWREV; +EXPORT_SYMBOL(HWREV); + +static void __init p1_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_VA_CHIPID); + s3c24xx_init_clocks(24000000); + s5pv210_gpiolib_init(); + s3c24xx_init_uarts(p1_uartcfgs, ARRAY_SIZE(p1_uartcfgs)); + s5p_reserve_bootmem(p1_media_devs, ARRAY_SIZE(p1_media_devs), S5P_RANGE_MFC); +#ifdef CONFIG_MTD_ONENAND + s5p_device_onenand.name = "s5pc110-onenand"; +#endif +} + +unsigned int pm_debug_scratchpad; + +static unsigned int ram_console_start; +static unsigned int ram_console_size; + +static void __init p1_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, + struct meminfo *mi) +{ + mi->bank[0].start = 0x30000000; + mi->bank[0].size = 80 * SZ_1M; + + mi->bank[1].start = 0x40000000; + mi->bank[1].size = 256 * SZ_1M; + + mi->bank[2].start = 0x50000000; + mi->bank[2].size = 255 * SZ_1M; + mi->nr_banks = 3; + + /* 1M for ram_console buffer */ + ram_console_start = mi->bank[2].start + mi->bank[2].size; + ram_console_size = SZ_1M - SZ_4K; + + pm_debug_scratchpad = ram_console_start + ram_console_size; +} + +/* this function are used to detect s5pc110 chip version temporally */ +int s5pc110_version ; + +void _hw_version_check(void) +{ + void __iomem *phy_address ; + int temp; + + phy_address = ioremap(0x40, 1); + + temp = __raw_readl(phy_address); + + if (temp == 0xE59F010C) + s5pc110_version = 0; + else + s5pc110_version = 1; + + printk(KERN_INFO "S5PC110 Hardware version : EVT%d\n", + s5pc110_version); + + iounmap(phy_address); +} + +/* + * Temporally used + * return value 0 -> EVT 0 + * value 1 -> evt 1 + */ + +int hw_version_check(void) +{ + return s5pc110_version ; +} +EXPORT_SYMBOL(hw_version_check); + +static void p1_init_gpio(void) +{ + s3c_config_gpio_table(); + s3c_config_sleep_gpio_table(ARRAY_SIZE(p1_sleep_gpio_table), + p1_sleep_gpio_table); +} + +static void __init fsa9480_gpio_init(void) +{ + s3c_gpio_cfgpin(GPIO_USB_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_USB_SEL, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_UART_SEL, S3C_GPIO_OUTPUT); + s3c_gpio_setpull(GPIO_UART_SEL, S3C_GPIO_PULL_NONE); + + s3c_gpio_cfgpin(GPIO_JACK_nINT, S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(GPIO_JACK_nINT, S3C_GPIO_PULL_NONE); +} + +static void __init setup_ram_console_mem(void) +{ + ram_console_resource[0].start = ram_console_start; + ram_console_resource[0].end = ram_console_start + ram_console_size - 1; +} + +static unsigned int p1_get_hwrev(void) +{ + unsigned int model_rev = 0; + unsigned int hw_rev = 0; + unsigned char model_str[12]; + + // Read HWREV_MODE gpio status + s3c_gpio_cfgpin(GPIO_HWREV_MODE0, S3C_GPIO_INPUT); + s3c_gpio_setpull( GPIO_HWREV_MODE0, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE1, S3C_GPIO_INPUT); + s3c_gpio_setpull( GPIO_HWREV_MODE1, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE2, S3C_GPIO_INPUT); + s3c_gpio_setpull( GPIO_HWREV_MODE2, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE3, S3C_GPIO_INPUT); + s3c_gpio_setpull( GPIO_HWREV_MODE3, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE4, S3C_GPIO_INPUT); + s3c_gpio_setpull( GPIO_HWREV_MODE4, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_HWREV_MODE5, S3C_GPIO_INPUT); + s3c_gpio_setpull( GPIO_HWREV_MODE5, S3C_GPIO_PULL_NONE); + + hw_rev = gpio_get_value(GPIO_HWREV_MODE0); + hw_rev = hw_rev | (gpio_get_value(GPIO_HWREV_MODE1) <<1); + hw_rev = hw_rev | (gpio_get_value(GPIO_HWREV_MODE2) <<2); + hw_rev = hw_rev | (gpio_get_value(GPIO_HWREV_MODE3) <<3); + + model_rev = (gpio_get_value(GPIO_HWREV_MODE4) << 1) | gpio_get_value(GPIO_HWREV_MODE5); + switch(model_rev) + { + case 0 : + sprintf(model_str, "P1_AMOLED"); + break; + case 1: + sprintf(model_str, "P2"); + break; + case 2: +#if defined(CONFIG_SAMSUNG_P1) + sprintf(model_str, "P1"); +#elif defined(CONFIG_SAMSUNG_P1C) + sprintf(model_str, "P1C"); +#elif defined(CONFIG_SAMSUNG_P1LN) + sprintf(model_str, "P1LN"); +#endif + break; + case 3: + sprintf(model_str, "P1"); + break; + default: + sprintf(model_str, "Unknown"); + break; + } + + if(model_rev == 0x2) // GT-P1000 + hw_rev += 6; // Rev0.6 + + printk(KERN_NOTICE "%s: HWREV (0x%x), Model (%s)\n", __func__, hw_rev, model_str); + + return hw_rev; +} + +static bool console_flushed; + +static void flush_console(void) +{ + if (console_flushed) + return; + + console_flushed = true; + + printk("\n"); + pr_emerg("Restarting %s\n", linux_banner); + if (!is_console_locked()) + return; + + mdelay(50); + + local_irq_disable(); + if (console_trylock()) + pr_emerg("flush_console: console was locked! busting!\n"); + else + pr_emerg("flush_console: console was locked!\n"); + console_unlock(); +} + +static void p1_pm_restart(char mode, const char *cmd) +{ + flush_console(); + + /* On a normal reboot, INFORM6 will contain a small integer + * reason code from the notifier hook. On a panic, it will + * contain the 0xee we set at boot. Write 0xbb to differentiate + * a watchdog-timeout-and-reboot (0xee) from a controlled reboot + * (0xbb) + */ + if (__raw_readl(S5P_INFORM6) == 0xee) + __raw_writel(0xbb, S5P_INFORM6); + + arm_machine_restart(mode, cmd); +} + +// Ugly hack to inject parameters (e.g. device serial, bootmode) into /proc/cmdline +static void __init p1_inject_cmdline(void) { + char *new_command_line; + int bootmode = __raw_readl(S5P_INFORM6); + int size; + + size = strlen(boot_command_line); + new_command_line = kmalloc(size + 40 + 11, GFP_KERNEL); + strcpy(new_command_line, saved_command_line); + size += sprintf(new_command_line + size, " androidboot.serialno=%08X%08X", + system_serial_high, system_serial_low); + + // Only write bootmode when less than 10 to prevent confusion with watchdog + // reboot (0xee = 238) + if (bootmode < 10) { + size += sprintf(new_command_line + size, " bootmode=%d", bootmode); + } + + saved_command_line = new_command_line; +} + +static void __init p1_machine_init(void) +{ + arm_pm_restart = p1_pm_restart; + setup_ram_console_mem(); + p1_inject_cmdline(); + platform_add_devices(p1_devices, ARRAY_SIZE(p1_devices)); + + /* Find out S5PC110 chip version */ + _hw_version_check(); + + pm_power_off = p1_power_off ; + + HWREV = p1_get_hwrev(); + printk(KERN_INFO "HWREV is 0x%x\n", HWREV); + + if(HWREV < P1_HWREV_REV06) + { + printk(KERN_ERR "This board is not supported: HWREV=0x%x\n", HWREV); + } + + /*initialise the gpio's*/ + p1_init_gpio(); + +#ifdef CONFIG_ANDROID_PMEM + android_pmem_set_platdata(); +#endif + + gpio_request(GPIO_TOUCH_EN, "touch en"); + + /* i2c */ + s3c_i2c0_set_platdata(NULL); + s3c_i2c1_set_platdata(NULL); + s3c_i2c2_set_platdata(NULL); + + l3g4200d_irq_init(); + + i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); + i2c_register_board_info(2, i2c_devs2, ARRAY_SIZE(i2c_devs2)); + + /* wm8994 codec */ + i2c_register_board_info(4, i2c_devs4, ARRAY_SIZE(i2c_devs4)); + + /* accel and gyro sensor */ + if(HWREV < P1_HWREV_REV09) + i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5)); + else + { + i2c_devs5[ARRAY_SIZE(i2c_devs5)-1].addr += 1; // From HW rev 0.9, slave addres is changed from 0x68 to 0x69 + i2c_register_board_info(5, i2c_devs5, ARRAY_SIZE(i2c_devs5)); + } + /* magnetic and light sensor */ + i2c_register_board_info(10, i2c_devs10, ARRAY_SIZE(i2c_devs10)); + + i2c_register_board_info(6, i2c_devs6, ARRAY_SIZE(i2c_devs6)); + /* FSA9480 */ + fsa9480_gpio_init(); + i2c_register_board_info(7, i2c_devs7, ARRAY_SIZE(i2c_devs7)); + + /* max17042 */ + max17042_gpio_init(); + i2c_register_board_info(9, i2c_devs9, ARRAY_SIZE(i2c_devs9)); + + /* smb136 */ + smb136_gpio_init(); + i2c_register_board_info(11, i2c_devs11, ARRAY_SIZE(i2c_devs11)); + + /* cmc623 */ + i2c_register_board_info(13, i2c_devs13, ARRAY_SIZE(i2c_devs13)); + +#if defined (CONFIG_VIDEO_NM6XX) + i2c_register_board_info(15, i2c_devs15, ARRAY_SIZE(i2c_devs15)); +#endif + +#ifdef CONFIG_FB_S3C_LVDS +#if defined(CONFIG_FB_S3C_CMC623) + platform_device_register(&cmc623_pwm_backlight); +#endif + platform_device_register(&sec_device_lms700); + s3cfb_set_platdata(&lvds_data); +#endif + +#if defined(CONFIG_S5P_ADC) + s3c_adc_set_platdata(&s3c_adc_platform); +#endif + +#if defined(CONFIG_PM) + s3c_pm_init(); +#endif + +#ifdef CONFIG_VIDEO_FIMC + /* fimc */ + s3c_fimc0_set_platdata(&fimc_plat_lsi); + s3c_fimc1_set_platdata(&fimc_plat_lsi); + s3c_fimc2_set_platdata(&fimc_plat_lsi); +#endif + +#ifdef CONFIG_VIDEO_JPEG_V2 + s3c_jpeg_set_platdata(&jpeg_plat); +#endif + +#ifdef CONFIG_VIDEO_MFC50 + /* mfc */ + s3c_mfc_set_platdata(NULL); +#endif + +#ifdef CONFIG_S3C_DEV_HSMMC + s5pv210_default_sdhci0(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC1 + s5pv210_default_sdhci1(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC2 + s5pv210_default_sdhci2(); +#endif +#ifdef CONFIG_S3C_DEV_HSMMC3 + s5pv210_default_sdhci3(); +#endif +#ifdef CONFIG_S5PV210_SETUP_SDHCI + s3c_sdhci_set_platdata(); +#endif + +#ifdef CONFIG_CPU_FREQ + s5pv210_cpufreq_set_platdata(&smdkc110_cpufreq_plat); +#endif + + regulator_has_full_constraints(); + + register_reboot_notifier(&p1_reboot_notifier); + + p1_switch_init(); + +#if defined(CONFIG_PHONE_P1_GSM) + gps_gpio_init(); +#endif + + uart_switch_init(); + + p1_init_wifi_mem(); + + qt_touch_init(); + + +#if defined (CONFIG_VIDEO_NM6XX) + nmi_i2s_cfg_gpio_init(); +#elif defined (CONFIG_SAMSUNG_P1LN) + nmi_pwr_disable(); // Disable the ISDBT PWR : Only Latin HW 0.3 +#endif + +#ifdef CONFIG_VIDEO_TV20 + platform_device_register(&s5p_device_tvout); + platform_device_register(&s5p_device_cec); + platform_device_register(&s5p_device_hpd); +#endif +#ifdef CONFIG_30PIN_CONN + platform_device_register(&sec_device_connector); +#endif + + /* write something into the INFORM6 register that we can use to + * differentiate an unclear reboot from a clean reboot (which + * writes a small integer code to INFORM6). + */ + __raw_writel(0xee, S5P_INFORM6); +} + +#ifdef CONFIG_USB_SUPPORT +/* Initializes OTG Phy. */ +void otg_phy_init(void) +{ + /* USB PHY0 Enable */ + writel(readl(S5P_USB_PHY_CONTROL) | (0x1<<0), + S5P_USB_PHY_CONTROL); + writel((readl(S3C_USBOTG_PHYPWR) & ~(0x3<<3) & ~(0x1<<0)) | (0x1<<5), + S3C_USBOTG_PHYPWR); + writel((readl(S3C_USBOTG_PHYCLK) & ~(0x5<<2)) | (0x3<<0), + S3C_USBOTG_PHYCLK); + writel((readl(S3C_USBOTG_RSTCON) & ~(0x3<<1)) | (0x1<<0), + S3C_USBOTG_RSTCON); + msleep(1); + writel(readl(S3C_USBOTG_RSTCON) & ~(0x7<<0), + S3C_USBOTG_RSTCON); + msleep(1); + + /* rising/falling time */ + writel(readl(S3C_USBOTG_PHYTUNE) | (0x1<<20), + S3C_USBOTG_PHYTUNE); + + /* set DC level as 6 (6%) */ + writel((readl(S3C_USBOTG_PHYTUNE) & ~(0xf)) | (0x1<<2) | (0x1<<1), + S3C_USBOTG_PHYTUNE); +} +EXPORT_SYMBOL(otg_phy_init); + +/* USB Control request data struct must be located here for DMA transfer */ +struct usb_ctrlrequest usb_ctrl __attribute__((aligned(64))); + +/* OTG PHY Power Off */ +void otg_phy_off(void) +{ + writel(readl(S3C_USBOTG_PHYPWR) | (0x3<<3), + S3C_USBOTG_PHYPWR); + writel(readl(S5P_USB_PHY_CONTROL) & ~(1<<0), + S5P_USB_PHY_CONTROL); +} +EXPORT_SYMBOL(otg_phy_off); + +void usb_host_phy_init(void) +{ + struct clk *otg_clk; + + otg_clk = clk_get(NULL, "otg"); + clk_enable(otg_clk); + + if (readl(S5P_USB_PHY_CONTROL) & (0x1<<1)) + return; + + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) | (0x1<<1), + S5P_USB_PHY_CONTROL); + __raw_writel((__raw_readl(S3C_USBOTG_PHYPWR) + & ~(0x1<<7) & ~(0x1<<6)) | (0x1<<8) | (0x1<<5), + S3C_USBOTG_PHYPWR); + __raw_writel((__raw_readl(S3C_USBOTG_PHYCLK) & ~(0x1<<7)) | (0x3<<0), + S3C_USBOTG_PHYCLK); + __raw_writel((__raw_readl(S3C_USBOTG_RSTCON)) | (0x1<<4) | (0x1<<3), + S3C_USBOTG_RSTCON); + __raw_writel(__raw_readl(S3C_USBOTG_RSTCON) & ~(0x1<<4) & ~(0x1<<3), + S3C_USBOTG_RSTCON); +} +EXPORT_SYMBOL(usb_host_phy_init); + +void usb_host_phy_off(void) +{ + __raw_writel(__raw_readl(S3C_USBOTG_PHYPWR) | (0x1<<7)|(0x1<<6), + S3C_USBOTG_PHYPWR); + __raw_writel(__raw_readl(S5P_USB_PHY_CONTROL) & ~(1<<1), + S5P_USB_PHY_CONTROL); +} +EXPORT_SYMBOL(usb_host_phy_off); +#endif + +#if defined(CONFIG_SAMSUNG_P1) +MACHINE_START(P1, "P1") +#elif defined(CONFIG_SAMSUNG_P1C) +MACHINE_START(P1, "P1C") +#elif defined(CONFIG_SAMSUNG_P1LN) +MACHINE_START(P1, "P1LN") +#endif + .boot_params = S5P_PA_SDRAM + 0x100, + .fixup = p1_fixup, + .init_irq = s5pv210_init_irq, + .map_io = p1_map_io, + .init_machine = p1_machine_init, + .timer = &s5p_systimer, +MACHINE_END + +void s3c_setup_uart_cfg_gpio(unsigned char port) +{ + switch (port) { + case 0: + s3c_gpio_cfgpin(GPIO_BT_RXD, S3C_GPIO_SFN(GPIO_BT_RXD_AF)); + s3c_gpio_setpull(GPIO_BT_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_TXD, S3C_GPIO_SFN(GPIO_BT_TXD_AF)); + s3c_gpio_setpull(GPIO_BT_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_CTS, S3C_GPIO_SFN(GPIO_BT_CTS_AF)); + s3c_gpio_setpull(GPIO_BT_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_BT_RTS, S3C_GPIO_SFN(GPIO_BT_RTS_AF)); + s3c_gpio_setpull(GPIO_BT_RTS, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_RXD, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_TXD, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_CTS, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_slp_cfgpin(GPIO_BT_RTS, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_BT_RTS, S3C_GPIO_PULL_NONE); + break; + case 1: + s3c_gpio_cfgpin(GPIO_GPS_RXD, S3C_GPIO_SFN(GPIO_GPS_RXD_AF)); + s3c_gpio_setpull(GPIO_GPS_RXD, S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(GPIO_GPS_TXD, S3C_GPIO_SFN(GPIO_GPS_TXD_AF)); + s3c_gpio_setpull(GPIO_GPS_TXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_CTS, S3C_GPIO_SFN(GPIO_GPS_CTS_AF)); + s3c_gpio_setpull(GPIO_GPS_CTS, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_GPS_RTS, S3C_GPIO_SFN(GPIO_GPS_RTS_AF)); + s3c_gpio_setpull(GPIO_GPS_RTS, S3C_GPIO_PULL_NONE); + break; + case 2: + s3c_gpio_cfgpin(GPIO_AP_RXD, S3C_GPIO_SFN(GPIO_AP_RXD_AF)); + s3c_gpio_setpull(GPIO_AP_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_AP_TXD, S3C_GPIO_SFN(GPIO_AP_TXD_AF)); + s3c_gpio_setpull(GPIO_AP_TXD, S3C_GPIO_PULL_NONE); + break; + case 3: + s3c_gpio_cfgpin(GPIO_FLM_RXD, S3C_GPIO_SFN(GPIO_FLM_RXD_AF)); + s3c_gpio_setpull(GPIO_FLM_RXD, S3C_GPIO_PULL_NONE); + s3c_gpio_cfgpin(GPIO_FLM_TXD, S3C_GPIO_SFN(GPIO_FLM_TXD_AF)); + s3c_gpio_setpull(GPIO_FLM_TXD, S3C_GPIO_PULL_NONE); + break; + default: + break; + } +} +EXPORT_SYMBOL(s3c_setup_uart_cfg_gpio); diff --git a/arch/arm/mach-s5pv210/p1-rfkill.c b/arch/arm/mach-s5pv210/p1-rfkill.c new file mode 100644 index 0000000..b453d33 --- /dev/null +++ b/arch/arm/mach-s5pv210/p1-rfkill.c @@ -0,0 +1,485 @@ +/* + * Copyright (C) 2010 Samsung Electronics Co., Ltd. + * + * Copyright (C) 2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Modified for Crespo on August, 2010 By Samsung Electronics Co. + * This is modified operate according to each status. + * + */ + +/* Control bluetooth power for Crespo platform */ + +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/rfkill.h> +#include <linux/delay.h> +#include <linux/types.h> +#include <linux/wakelock.h> +#include <linux/irq.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <mach/gpio.h> +#include <mach/gpio-p1.h> +#include <mach/hardware.h> +#include <plat/gpio-cfg.h> +#include <plat/irqs.h> +#include "herring.h" + +#define BT_SLEEP_ENABLE +#define USE_LOCK_DVFS + +#define IRQ_BT_HOST_WAKE IRQ_EINT(21) + +#ifndef GPIO_LEVEL_LOW +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 +#endif + +static struct wake_lock rfkill_wake_lock; +static struct rfkill *bt_rfk; + +static const char bt_name[] = "bcm4329"; +static bool current_blocked = true; + +#ifdef BT_SLEEP_ENABLE +static struct wake_lock bt_wake_lock; +static struct rfkill *bt_sleep_rfk; +#endif /* BT_SLEEP_ENABLE */ + +#ifdef USE_LOCK_DVFS +static struct rfkill *bt_lock_dvfs_rfk; +static struct rfkill *bt_lock_dvfs_l2_rfk; +#include <mach/cpu-freq-v210.h> +#endif + +static int bluetooth_set_power(void *data, enum rfkill_user_states state) +{ + int ret = 0; + int irq; + /* BT Host Wake IRQ */ + irq = IRQ_BT_HOST_WAKE; + + switch (state) { + + case RFKILL_USER_STATE_UNBLOCKED: + pr_debug("[BT] Device Powering ON\n"); + + s3c_setup_uart_cfg_gpio(0); + + if (gpio_is_valid(GPIO_WLAN_BT_EN)) + gpio_direction_output(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + + if (gpio_is_valid(GPIO_BT_nRST)) + gpio_direction_output(GPIO_BT_nRST, GPIO_LEVEL_LOW); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + /* Set GPIO_BT_WLAN_REG_ON high */ + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_HIGH); + + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_WLAN_BT_EN = %d\n", + gpio_get_value(GPIO_WLAN_BT_EN)); + /* + * FIXME sleep should be enabled disabled since the device is + * not booting if its enabled + */ + /* + * 100msec, delay between reg_on & rst. + * (bcm4329 powerup sequence) + */ + msleep(100); + + /* Set GPIO_BT_nRST high */ + s3c_gpio_setpull(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_BT_nRST, GPIO_LEVEL_HIGH); + + s3c_gpio_slp_cfgpin(GPIO_BT_nRST, S3C_GPIO_SLP_OUT1); + s3c_gpio_slp_setpull_updown(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + /* + * 50msec, delay after bt rst + * (bcm4329 powerup sequence) + */ + msleep(50); + + ret = enable_irq_wake(irq); + if (ret < 0) + pr_err("[BT] set wakeup src failed\n"); + + enable_irq(irq); + break; + + case RFKILL_USER_STATE_SOFT_BLOCKED: + pr_debug("[BT] Device Powering OFF\n"); + + ret = disable_irq_wake(irq); + if (ret < 0) + pr_err("[BT] unset wakeup src failed\n"); + + disable_irq(irq); + wake_unlock(&rfkill_wake_lock); + + s3c_gpio_setpull(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_BT_nRST, GPIO_LEVEL_LOW); + + s3c_gpio_slp_cfgpin(GPIO_BT_nRST, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_BT_nRST, S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_BT_nRST = %d\n", + gpio_get_value(GPIO_BT_nRST)); + + if (gpio_get_value(GPIO_WLAN_nRST) == 0) { + s3c_gpio_setpull(GPIO_WLAN_BT_EN, S3C_GPIO_PULL_NONE); + gpio_set_value(GPIO_WLAN_BT_EN, GPIO_LEVEL_LOW); + + s3c_gpio_slp_cfgpin(GPIO_WLAN_BT_EN, S3C_GPIO_SLP_OUT0); + s3c_gpio_slp_setpull_updown(GPIO_WLAN_BT_EN, + S3C_GPIO_PULL_NONE); + + pr_debug("[BT] GPIO_WLAN_BT_EN = %d\n", + gpio_get_value(GPIO_WLAN_BT_EN)); + } + break; + + default: + pr_err("[BT] Bad bluetooth rfkill state %d\n", state); + } + + return 0; +} + +irqreturn_t bt_host_wake_irq_handler(int irq, void *dev_id) +{ + pr_debug("[BT] bt_host_wake_irq_handler start\n"); + + wake_lock_timeout(&rfkill_wake_lock, 5*HZ); + + return IRQ_HANDLED; +} + +static int bt_rfkill_set_block(void *data, bool blocked) +{ + unsigned int ret = 0; + + if (current_blocked == blocked) { + pr_debug("[BT] keeping current blocked state %d\n", blocked); + return ret; + } + + current_blocked = blocked; + + ret = bluetooth_set_power(data, blocked ? + RFKILL_USER_STATE_SOFT_BLOCKED : + RFKILL_USER_STATE_UNBLOCKED); + + return ret; +} + +static const struct rfkill_ops bt_rfkill_ops = { + .set_block = bt_rfkill_set_block, +}; + +#ifdef BT_SLEEP_ENABLE +static int bluetooth_set_sleep(void *data, enum rfkill_user_states state) +{ + switch (state) { + + case RFKILL_USER_STATE_UNBLOCKED: + gpio_set_value(GPIO_BT_WAKE, 0); + pr_debug("[BT] GPIO_BT_WAKE = %d\n", gpio_get_value(GPIO_BT_WAKE) ); + pr_debug("[BT] wake_unlock(bt_wake_lock)\n"); + wake_unlock(&bt_wake_lock); + break; + + case RFKILL_USER_STATE_SOFT_BLOCKED: + gpio_set_value(GPIO_BT_WAKE, 1); + pr_debug("[BT] GPIO_BT_WAKE = %d\n", gpio_get_value(GPIO_BT_WAKE) ); + pr_debug("[BT] wake_lock(bt_wake_lock)\n"); + wake_lock(&bt_wake_lock); + break; + + default: + pr_err("[BT] bad bluetooth rfkill state %d\n", state); + } + return 0; +} + +static int btsleep_rfkill_set_block(void *data, bool blocked) +{ + int ret =0; + + ret = bluetooth_set_sleep(data, blocked? + RFKILL_USER_STATE_SOFT_BLOCKED : + RFKILL_USER_STATE_UNBLOCKED); + + return ret; +} + +static const struct rfkill_ops btsleep_rfkill_ops = { + .set_block = btsleep_rfkill_set_block, +}; +#endif + +#ifdef USE_LOCK_DVFS +static int bluetooth_lock_dvfs(void *data, enum rfkill_user_states state) +{ + if(!gpio_get_value(GPIO_BT_nRST)) + return 0; + + switch (state) { + case RFKILL_USER_STATE_UNBLOCKED: + s5pv210_unlock_dvfs_high_level(DVFS_LOCK_TOKEN_9); + pr_debug("[BT] dvfs unlock\n"); + break; + case RFKILL_USER_STATE_SOFT_BLOCKED: + s5pv210_lock_dvfs_high_level(DVFS_LOCK_TOKEN_9, L3); + pr_debug("[BT] dvfs lock to L3\n"); + break; + case RFKILL_USER_STATE_HARD_BLOCKED: + s5pv210_lock_dvfs_high_level(DVFS_LOCK_TOKEN_9, L2); + pr_debug("[BT] dvfs lock to L2\n"); + break; + default: + pr_err("[BT] bad bluetooth rfkill state %d\n", state); + } + return 0; +} + +static int bt_lock_dvfs_rfkill_set_block(void *data, bool blocked) +{ + int ret =0; + + ret = bluetooth_lock_dvfs(data, blocked? + RFKILL_USER_STATE_SOFT_BLOCKED : + RFKILL_USER_STATE_UNBLOCKED); + + return ret; +} + +static int bt_lock_dvfs_l2_rfkill_set_block(void *data, bool blocked) +{ + int ret =0; + + ret = bluetooth_lock_dvfs(data, blocked? + RFKILL_USER_STATE_HARD_BLOCKED : + RFKILL_USER_STATE_UNBLOCKED); + + return ret; +} + + +static const struct rfkill_ops bt_lock_dvfs_rfkill_ops = { + .set_block = bt_lock_dvfs_rfkill_set_block, +}; + + +static const struct rfkill_ops bt_lock_dvfs_l2_rfkill_ops = { + .set_block = bt_lock_dvfs_l2_rfkill_set_block, +}; +#endif + +static int __init crespo_rfkill_probe(struct platform_device *pdev) +{ + int irq; + int ret; + + /* Initialize wake locks */ + wake_lock_init(&rfkill_wake_lock, WAKE_LOCK_SUSPEND, "bt_host_wake"); + + ret = gpio_request(GPIO_WLAN_BT_EN, "GPB"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_WLAN_BT_EN!\n"); + goto err_req_gpio_wlan_bt_en; + } + + ret = gpio_request(GPIO_BT_nRST, "GPB"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_BT_nRST!\n"); + goto err_req_gpio_bt_nrst; + } + + /* BT Host Wake IRQ */ + irq = IRQ_BT_HOST_WAKE; + + ret = request_irq(irq, bt_host_wake_irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "bt_host_wake_irq_handler", NULL); + + if (ret < 0) { + pr_err("[BT] Request_irq failed\n"); + goto err_req_irq; + } + + disable_irq(irq); + + bt_rfk = rfkill_alloc(bt_name, &pdev->dev, RFKILL_TYPE_BLUETOOTH, + &bt_rfkill_ops, NULL); + + if (!bt_rfk) { + pr_err("[BT] bt_rfk : rfkill_alloc is failed\n"); + ret = -ENOMEM; + goto err_alloc; + } + + rfkill_init_sw_state(bt_rfk, 0); + + pr_debug("[BT] rfkill_register(bt_rfk)\n"); + + ret = rfkill_register(bt_rfk); + if (ret) { + pr_err("********ERROR IN REGISTERING THE bt_rfk********\n"); + goto err_register; + } + + rfkill_set_sw_state(bt_rfk, 1); + bt_rfkill_set_block(NULL, true); + +#ifdef BT_SLEEP_ENABLE + wake_lock_init(&bt_wake_lock, WAKE_LOCK_SUSPEND, "bt_wake"); + + ret = gpio_request(GPIO_BT_WAKE, "gpio_bt_wake"); + if (ret < 0) { + pr_err("[BT] Failed to request GPIO_BT_WAKE\n"); + goto err_req_gpio_bt_wake; + } + + gpio_direction_output(GPIO_BT_WAKE, GPIO_LEVEL_LOW); + + bt_sleep_rfk = rfkill_alloc(bt_name, &pdev->dev, RFKILL_TYPE_BLUETOOTH, + &btsleep_rfkill_ops, NULL); + + if (!bt_sleep_rfk) { + pr_err("[BT] bt_sleep_rfk : rfkill_alloc is failed\n"); + ret = -ENOMEM; + goto err_sleep_alloc; + } + + rfkill_set_sw_state(bt_sleep_rfk, 1); + + pr_debug("[BT] rfkill_register(bt_sleep_rfk)\n"); + + ret = rfkill_register(bt_sleep_rfk); + if (ret) { + pr_err("********ERROR IN REGISTERING THE bt_sleep_rfk********\n"); + goto err_sleep_register; + } +#endif + +#ifdef USE_LOCK_DVFS + bt_lock_dvfs_rfk = rfkill_alloc(bt_name, &pdev->dev, RFKILL_TYPE_BLUETOOTH, + &bt_lock_dvfs_rfkill_ops, NULL); + + if (!bt_lock_dvfs_rfk) { + pr_err("[BT] bt_lock_dvfs_rfk : rfkill_alloc is failed\n"); + ret = -ENOMEM; + goto err_dvfs_lock_alloc; + } + + pr_debug("[BT] rfkill_register(bt_lock_dvfs_rfk)\n"); + + ret = rfkill_register(bt_lock_dvfs_rfk); + if (ret) { + pr_err("********ERROR IN REGISTERING THE bt_lock_dvfs_rfk********\n"); + goto err_lock_dvfs_register; + } + + bt_lock_dvfs_l2_rfk = rfkill_alloc(bt_name, &pdev->dev, RFKILL_TYPE_BLUETOOTH, + &bt_lock_dvfs_l2_rfkill_ops, NULL); + + if (!bt_lock_dvfs_l2_rfk) { + pr_err("[BT] bt_lock_dvfs_l2_rfk : rfkill_alloc is failed\n"); + ret = -ENOMEM; + goto err_dvfs_l2_lock_alloc; + } + + pr_debug("[BT] rfkill_register(bt_lock_dvfs_l2_rfk)\n"); + + ret = rfkill_register(bt_lock_dvfs_l2_rfk); + if (ret) { + pr_err("********ERROR IN REGISTERING THE bt_lock_dvfs_l2_rfk********\n"); + goto err_lock_dvfs_l2_register; + } +#endif + return ret; + +#ifdef USE_LOCK_DVFS +err_lock_dvfs_l2_register: + rfkill_destroy(bt_lock_dvfs_l2_rfk); + +err_dvfs_l2_lock_alloc: + rfkill_unregister(bt_lock_dvfs_rfk); + +err_lock_dvfs_register: + rfkill_destroy(bt_lock_dvfs_rfk); + +err_dvfs_lock_alloc: + rfkill_unregister(bt_sleep_rfk); +#endif + +#ifdef BT_SLEEP_ENABLE +err_sleep_register: + rfkill_destroy(bt_sleep_rfk); + +err_sleep_alloc: + gpio_free(GPIO_BT_WAKE); + +err_req_gpio_bt_wake: + rfkill_unregister(bt_rfk); +#endif + + err_register: + rfkill_destroy(bt_rfk); + + err_alloc: + free_irq(irq, NULL); + + err_req_irq: + gpio_free(GPIO_BT_nRST); + + err_req_gpio_bt_nrst: + gpio_free(GPIO_WLAN_BT_EN); + + err_req_gpio_wlan_bt_en: + return ret; +} + +static struct platform_driver crespo_device_rfkill = { + .probe = crespo_rfkill_probe, + .driver = { + .name = "bt_rfkill", + .owner = THIS_MODULE, + }, +}; + +static int __init crespo_rfkill_init(void) +{ + int rc = 0; + rc = platform_driver_register(&crespo_device_rfkill); + + return rc; +} + +module_init(crespo_rfkill_init); +MODULE_DESCRIPTION("crespo rfkill"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/p1-sec_switch.c b/arch/arm/mach-s5pv210/p1-sec_switch.c new file mode 100644 index 0000000..0de99e0 --- /dev/null +++ b/arch/arm/mach-s5pv210/p1-sec_switch.c @@ -0,0 +1,353 @@ +/* + * UART/USB path switching driver for Samsung Electronics devices. + * + * Copyright (C) 2010 Samsung Electronics + * Ikkeun Kim <iks.kim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/switch.h> +#include <mach/param.h> +#include <linux/fsa9480.h> +#include <linux/sec_battery.h> +#include <asm/mach/arch.h> +#include <linux/regulator/consumer.h> +#include <mach/gpio.h> +#include <mach/gpio-p1.h> +#include <mach/sec_switch.h> +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> +#include <plat/gpio-cfg.h> +#include <linux/moduleparam.h> + + +struct sec_switch_struct { + struct sec_switch_platform_data *pdata; + int switch_sel; + int uart_owner; +}; + +struct sec_switch_wq { + struct delayed_work work_q; + struct sec_switch_struct *sdata; + struct list_head entry; +}; + +extern struct device *switch_dev; +static int switchsel; +static struct kernel_param_ops param_ops_switchsel = { + .set = param_set_int, + .get = param_get_int, +}; + +// Get SWITCH_SEL param value from kernel CMDLINE parameter. +__module_param_call("", switchsel, ¶m_ops_switchsel, &switchsel, 0, 0444); +MODULE_PARM_DESC(switchsel, "Switch select parameter value."); + + +static void usb_switch_mode(struct sec_switch_struct *secsw, int mode
) +{ + if(mode == SWITCH_PDA) + { + if(secsw->pdata && secsw->pdata->set_regulator) + secsw->pdata->set_regulator(AP_VBUS_ON); + mdelay(10); + + fsa9480_manual_switching(AUTO_SWITCH); + } + else // SWITCH_MODEM + { + if(secsw->pdata && secsw->pdata->set_regulator) + secsw->pdata->set_regulator(CP_VBUS_ON); + mdelay(10); + + fsa9480_manual_switching(SWITCH_V_Audio_Port); + } +} + +/* for sysfs control (/sys/class/sec/switch/usb_sel) */ +static ssize_t usb_sel_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + int usb_path = secsw->switch_sel & (int)(USB_SEL_MASK); + + return sprintf(buf, "USB Switch : %s\n", usb_path==SWITCH_PDA?"PDA":"MODEM"); +} + +static ssize_t usb_sel_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + + printk("\n"); + + if (sec_get_param_value) + sec_get_param_value(__SWITCH_SEL, &(secsw->switch_sel)); + + if(strncmp(buf, "PDA", 3) == 0 || strncmp(buf, "pda", 3) == 0) { + usb_switch_mode(secsw, SWITCH_PDA); +// usb_switching_value_update(SWITCH_PDA); + secsw->switch_sel |= USB_SEL_MASK; + } + + if(strncmp(buf, "MODEM", 5) == 0 || strncmp(buf, "modem", 5) == 0) { + usb_switch_mode(secsw, SWITCH_MODEM); +// usb_switching_value_update(SWITCH_MODEM); + secsw->switch_sel &= ~USB_SEL_MASK; + } + +// switching_value_update(); + + if (sec_set_param_value) + sec_set_param_value(__SWITCH_SEL, &(secsw->switch_sel)); + + // update shared variable. + if(secsw->pdata && secsw->pdata->set_switch_status) + secsw->pdata->set_switch_status(secsw->switch_sel); + + return size; +} + +static DEVICE_ATTR(usb_sel, 0664, usb_sel_show, usb_sel_store); + + +static ssize_t uart_switch_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + + if (secsw->uart_owner) + return sprintf(buf, "[UART Switch] Current UART owner = PDA \n"); + else + return sprintf(buf, "[UART Switch] Current UART owner = MODEM \n"); +} + +static ssize_t uart_switch_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + + if (sec_get_param_value) + sec_get_param_value(__SWITCH_SEL, &(secsw->switch_sel)); + + if (strncmp(buf, "PDA", 3) == 0 || strncmp(buf, "pda", 3) == 0) { + gpio_set_value(GPIO_UART_SEL, 1); +// uart_switching_value_update(SWITCH_PDA); + secsw->uart_owner = 1; + secsw->switch_sel |= UART_SEL_MASK; + printk("[UART Switch] Path : PDA\n"); + } + + if (strncmp(buf, "MODEM", 5) == 0 || strncmp(buf, "modem", 5) == 0) { + gpio_set_value(GPIO_UART_SEL, 0); +// uart_switching_value_update(SWITCH_MODEM); + secsw->uart_owner = 0; + secsw->switch_sel &= ~UART_SEL_MASK; + printk("[UART Switch] Path : MODEM\n"); + } + +// switching_value_update(); + + if (sec_set_param_value) + sec_set_param_value(__SWITCH_SEL, &(secsw->switch_sel)); + + // update shared variable. + if(secsw->pdata && secsw->pdata->set_switch_status) + secsw->pdata->set_switch_status(secsw->switch_sel); + + return size; +} + +static DEVICE_ATTR(uart_sel, 0664, uart_switch_show, uart_switch_store); + + +// for sysfs control (/sys/class/sec/switch/usb_state) +static ssize_t usb_state_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + int cable_state = CABLE_TYPE_NONE; + + if(secsw->pdata && secsw->pdata->get_cable_status) + cable_state = secsw->pdata->get_cable_status(); + + return sprintf(buf, "%s\n", (cable_state==CABLE_TYPE_USB)?"USB_STATE_CONFIGURED":"USB_STATE_NOTCONFIGURED"); +} + +static ssize_t usb_state_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) +{ + printk("\n"); + return size; +} + +static DEVICE_ATTR(usb_state, 0664, usb_state_show, usb_state_store); + + +// for sysfs control (/sys/class/sec/switch/disable_vbus) +static ssize_t disable_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + printk("\n"); + return 0; +} + +static ssize_t disable_vbus_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(dev); + printk("%s\n", __func__); + if(secsw->pdata && secsw->pdata->set_regulator) + secsw->pdata->set_regulator(AP_VBUS_OFF); + + return size; +} + +static DEVICE_ATTR(disable_vbus, 0664, disable_vbus_show, disable_vbus_store); + + +static void sec_switch_init_work(struct work_struct *work) +{ + struct delayed_work *dw = container_of(work, struct delayed_work, work); + struct sec_switch_wq *wq = container_of(dw, struct sec_switch_wq, work_q); + struct sec_switch_struct *secsw = wq->sdata; + int usb_sel = 0; + int uart_sel = 0; + int ret = 0; + +// printk("%s : called!!\n", __func__); + + if (!regulator_get(NULL, "vbus_ap") || !(secsw->pdata->get_phy_init_status())) { + schedule_delayed_work(&wq->work_q, msecs_to_jiffies(100)); + return ; + } + else { + cancel_delayed_work(&wq->work_q); + } + + if(secsw->pdata && secsw->pdata->get_regulator) { + ret = secsw->pdata->get_regulator(); + if(ret != 0) { + pr_err("%s : failed to get regulators\n", __func__); + return ; + } + } + + // init shared variable. + if(secsw->pdata && secsw->pdata->set_switch_status) + secsw->pdata->set_switch_status(secsw->switch_sel); + + usb_sel = secsw->switch_sel & (int)(USB_SEL_MASK); + uart_sel = (secsw->switch_sel & (int)(UART_SEL_MASK)) >> 1; + + printk("%s : initial usb_sel(%d), uart_sel(%d)\n", __func__, usb_sel, uart_sel); + + // init UART/USB path. + if(usb_sel) { + usb_switch_mode(secsw, SWITCH_PDA); + } + else { + usb_switch_mode(secsw, SWITCH_MODEM); + } + + if(uart_sel) { + gpio_set_value(GPIO_UART_SEL, 1); + secsw->uart_owner = 1; + } + else { + gpio_set_value(GPIO_UART_SEL, 0); + secsw->uart_owner = 0; + } + +} + +static int sec_switch_probe(struct platform_device *pdev) +{ + struct sec_switch_struct *secsw; + struct sec_switch_platform_data *pdata = pdev->dev.platform_data; + struct sec_switch_wq *wq; + + + if (!pdata) { + pr_err("%s : pdata is NULL.\n", __func__); + return -ENODEV; + } + + secsw = kzalloc(sizeof(struct sec_switch_struct), GFP_KERNEL); + if (!secsw) { + pr_err("%s : failed to allocate memory\n", __func__); + return -ENOMEM; + } + + printk("%s : *** switch_sel (0x%x)\n", __func__, switchsel); + + secsw->pdata = pdata; + secsw->switch_sel = switchsel; + + dev_set_drvdata(switch_dev, secsw); + + // create sysfs files. + if (device_create_file(switch_dev, &dev_attr_uart_sel) < 0) + pr_err("Failed to create device file(%s)!\n", dev_attr_uart_sel.attr.name); + + if (device_create_file(switch_dev, &dev_attr_usb_sel) < 0) + pr_err("Failed to create device file(%s)!\n", dev_attr_usb_sel.attr.name); + + if (device_create_file(switch_dev, &dev_attr_usb_state) < 0) + pr_err("Failed to create device file(%s)!\n", dev_attr_usb_state.attr.name); + + if (device_create_file(switch_dev, &dev_attr_disable_vbus) < 0) + pr_err("Failed to create device file(%s)!\n", dev_attr_disable_vbus.attr.name); + + // run work queue + wq = kmalloc(sizeof(struct sec_switch_wq), GFP_ATOMIC); + if (wq) { + wq->sdata = secsw; + INIT_DELAYED_WORK(&wq->work_q, sec_switch_init_work); + schedule_delayed_work(&wq->work_q, msecs_to_jiffies(100)); + } + else + return -ENOMEM; + + return 0; +} + +static int sec_switch_remove(struct platform_device *pdev) +{ + struct sec_switch_struct *secsw = dev_get_drvdata(&pdev->dev); + + kfree(secsw); + + return 0; +} + +static struct platform_driver sec_switch_driver = { + .probe = sec_switch_probe, + .remove = sec_switch_remove, + .driver = { + .name = "sec_switch", + .owner = THIS_MODULE, + }, +}; + +static int __init sec_switch_init(void) +{ + return platform_driver_register(&sec_switch_driver); +} + +static void __exit sec_switch_exit(void) +{ + platform_driver_unregister(&sec_switch_driver); +} + +module_init(sec_switch_init); +module_exit(sec_switch_exit); + +MODULE_AUTHOR("Ikkeun Kim <iks.kim@samsung.com>"); +MODULE_DESCRIPTION("Samsung Electronics Corp Switch driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/p1-watchdog.c b/arch/arm/mach-s5pv210/p1-watchdog.c new file mode 100644 index 0000000..06cc460 --- /dev/null +++ b/arch/arm/mach-s5pv210/p1-watchdog.c @@ -0,0 +1,111 @@ +/* p1-watchdog.c + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <plat/regs-watchdog.h> +#include <mach/map.h> + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/cpufreq.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/workqueue.h> +#include <linux/io.h> + +/* reset timeout in PCLK/256/128 (~2048:1s) */ +static unsigned watchdog_reset = (30 * 2048); + +/* pet timeout in jiffies */ +static unsigned watchdog_pet = (10 * HZ); + +static struct workqueue_struct *watchdog_wq; +static void watchdog_workfunc(struct work_struct *work); +static DECLARE_DELAYED_WORK(watchdog_work, watchdog_workfunc); + +static void watchdog_workfunc(struct work_struct *work) +{ + writel(watchdog_reset, S3C2410_WTCNT); + queue_delayed_work(watchdog_wq, &watchdog_work, watchdog_pet); +} + +static void watchdog_start(void) +{ + unsigned int val; + + /* set to PCLK / 256 / 128 */ + val = S3C2410_WTCON_DIV128; + val |= S3C2410_WTCON_PRESCALE(255); + writel(val, S3C2410_WTCON); + + /* program initial count */ + writel(watchdog_reset, S3C2410_WTCNT); + writel(watchdog_reset, S3C2410_WTDAT); + + /* start timer */ + val |= S3C2410_WTCON_RSTEN | S3C2410_WTCON_ENABLE; + writel(val, S3C2410_WTCON); + + /* make sure we're ready to pet the dog */ + queue_delayed_work(watchdog_wq, &watchdog_work, watchdog_pet); +} + +static void watchdog_stop(void) +{ + writel(0, S3C2410_WTCON); +} + +static int watchdog_probe(struct platform_device *pdev) +{ + watchdog_wq = alloc_workqueue("pet_watchdog", + WQ_UNBOUND | WQ_HIGHPRI, 1); + watchdog_start(); + return 0; +} + +static int watchdog_suspend(struct device *dev) +{ + watchdog_stop(); + return 0; +} + +static int watchdog_resume(struct device *dev) +{ + watchdog_start(); + return 0; +} + +static struct dev_pm_ops watchdog_pm_ops = { + .suspend_noirq = watchdog_suspend, + .resume_noirq = watchdog_resume, +}; + +static struct platform_driver watchdog_driver = { + .probe = watchdog_probe, + .driver = { + .owner = THIS_MODULE, + .name = "watchdog", + .pm = &watchdog_pm_ops, + }, +}; + +static int __init watchdog_init(void) +{ + return platform_driver_register(&watchdog_driver); +} + +module_init(watchdog_init); diff --git a/arch/arm/mach-s5pv210/sec_jack.c b/arch/arm/mach-s5pv210/sec_jack.c new file mode 100644 index 0000000..9609dee --- /dev/null +++ b/arch/arm/mach-s5pv210/sec_jack.c @@ -0,0 +1,675 @@ +/* + * JACK device detection driver. + * + * Copyright (C) 2009 Samsung Electronics, Inc. + * + * Authors: + * Uk Kim <w0806.kim@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include <linux/module.h> +#include <linux/sysdev.h> +#include <linux/fs.h> +#include <linux/interrupt.h> +#include <linux/workqueue.h> +#include <linux/irq.h> +#include <linux/delay.h> +#include <linux/types.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#include <linux/mutex.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/switch.h> +#include <linux/input.h> +#include <linux/timer.h> +#include <linux/wakelock.h> +#include <linux/slab.h> + +#include <mach/hardware.h> +#include <mach/gpio-p1.h> +#include <mach/gpio.h> +#include <mach/regs-gpio.h> +#include <plat/gpio-cfg.h> +#include <plat/irqs.h> +#include <asm/mach-types.h> + +#include <mach/sec_jack.h> + +#define CONFIG_DEBUG_SEC_JACK +#define SUBJECT "JACK_DRIVER" + +#ifdef CONFIG_DEBUG_SEC_JACK +#define SEC_JACKDEV_DBG(format,...)\ + printk ("[ "SUBJECT " (%s,%d) ] " format "\n", __func__, __LINE__, ## __VA_ARGS__); + +#else +#define DEBUG_LOG(format,...) +#endif + +#define KEYCODE_SENDEND 248 + +#define DETECTION_CHECK_COUNT 2 +#define DETECTION_CHECK_TIME get_jiffies_64() + (HZ/10)// 1000ms / 10 = 100ms +#define SEND_END_ENABLE_TIME get_jiffies_64() + (HZ*2) // 1000ms * 2 = 2sec + +#define SEND_END_CHECK_COUNT 3 +#define SEND_END_CHECK_TIME get_jiffies_64() + (HZ/50) //1000ms / 50 = 20ms + +#define WAKE_LOCK_TIME (HZ * 5) /* 5 sec */ + +static struct platform_driver sec_jack_driver; + +struct class *jack_class; +EXPORT_SYMBOL(jack_class); +static struct device *jack_selector_fs; // Sysfs device, this is used for communication with Cal App. +EXPORT_SYMBOL(jack_selector_fs); +extern int s3c_adc_get_adc_data(int channel); + +struct sec_jack_info { + struct sec_jack_port port; + struct input_dev *input; + int send_end_key_pressed; +}; + +static struct sec_jack_info *hi; + +struct switch_dev switch_jack_detection = { + .name = "h2w", +}; + +struct switch_dev switch_sendend = { + .name = "send_end", +}; + +static struct timer_list jack_detect_timer; +static struct timer_list send_end_key_event_timer; + +static unsigned int current_jack_type_status; +static unsigned int jack_detect_timer_token; +static unsigned int send_end_key_timer_token; +static unsigned int send_end_irq_token; +static struct wake_lock jack_sendend_wake_lock; + +short int get_headset_status(void) +{ + SEC_JACKDEV_DBG(" headset_status %d", current_jack_type_status); + return current_jack_type_status; +} + +EXPORT_SYMBOL(get_headset_status); + + +//WORK QUEING FUNCTION +static void jack_type_detect_change(struct work_struct *ignored) +{ + int adc = 0; + struct sec_gpio_info *det_jack = &hi->port.det_jack; + struct sec_gpio_info *send_end = &hi->port.send_end; + int state = gpio_get_value(det_jack->gpio) ^ det_jack->low_active; + + if (state) + { + adc = s3c_adc_get_adc_data(SEC_HEADSET_ADC_CHANNEL); + SEC_JACKDEV_DBG("headset detect : ADC value = %d\n", adc); + + + if(adc >= 0 && adc <= 400) + { + printk("3 pole headset attatched : adc = %d\n", adc); + current_jack_type_status = SEC_HEADSET_3_POLE_DEVICE; + + printk("EAR_MICBIAS Off\n"); + gpio_set_value(GPIO_EAR_MICBIAS0_EN, 0); + gpio_set_value(GPIO_EAR_MICBIAS_EN, 0); + } + else if(adc > 400 && adc <= 3100) + { + printk("4 pole headset attached : adc = %d\n", adc); + enable_irq (send_end->eint); + enable_irq_wake (send_end->eint); + + send_end_irq_token++; + current_jack_type_status = SEC_HEADSET_4_POLE_DEVICE; + } + else if(adc > 3100 && adc <= 3900) + { + printk("3 pole headset attatched : adc = %d\n", adc); + current_jack_type_status = SEC_HEADSET_3_POLE_DEVICE; + + printk("EAR_MICBIAS Off\n"); + gpio_set_value(GPIO_EAR_MICBIAS0_EN, 0); + gpio_set_value(GPIO_EAR_MICBIAS_EN, 0); + } + else + { + printk("jack detected but unknown device : adc = %d\n", adc); + current_jack_type_status = SEC_UNKNOWN_DEVICE; + } + + switch_set_state(&switch_jack_detection, current_jack_type_status); + } + else + { + printk(KERN_ALERT "Error : mic bias enable complete but headset detached!!\n"); + current_jack_type_status = SEC_JACK_NO_DEVICE; + + printk("EAR_MICBIAS Off\n"); + gpio_set_value(GPIO_EAR_MICBIAS0_EN, 0); + gpio_set_value(GPIO_EAR_MICBIAS_EN, 0); + } +} + +static DECLARE_DELAYED_WORK(detect_jack_type_work, jack_type_detect_change); + +static void jack_detect_change(struct work_struct *ignored) +{ + struct sec_gpio_info *det_jack = &hi->port.det_jack; + struct sec_gpio_info *send_end = &hi->port.send_end; + int state; + + SEC_JACKDEV_DBG(""); + del_timer(&jack_detect_timer); + cancel_delayed_work_sync(&detect_jack_type_work); + state = gpio_get_value(det_jack->gpio) ^ det_jack->low_active; + + if (state && !send_end_irq_token) + { + /* prevent suspend to allow user space to respond to switch */ + wake_lock_timeout(&jack_sendend_wake_lock, WAKE_LOCK_TIME); + SEC_JACKDEV_DBG("JACK dev attached timer start\n"); + jack_detect_timer_token = 0; + jack_detect_timer.expires = DETECTION_CHECK_TIME; + add_timer(&jack_detect_timer); + } + else if(!state) + { + printk("JACK dev detached %d \n", send_end_irq_token); + + if(send_end_irq_token > 0) + { + printk("EAR_MICBIAS Off\n"); + gpio_set_value(GPIO_EAR_MICBIAS0_EN, 0); + gpio_set_value(GPIO_EAR_MICBIAS_EN, 0); + + disable_irq (send_end->eint); + disable_irq_wake(send_end->eint); + + send_end_irq_token--; + + if(hi->send_end_key_pressed) + { + switch_set_state(&switch_sendend, 0); + input_report_key(hi->input, KEYCODE_SENDEND, 0); + input_sync(hi->input); + hi->send_end_key_pressed = 0; + printk("SEND/END is released by detached JACK \n"); + msleep(500); + } + } + + current_jack_type_status = SEC_JACK_NO_DEVICE; + switch_set_state(&switch_jack_detection, current_jack_type_status); + } + else + { + SEC_JACKDEV_DBG("Headset state does not valid. or send_end event"); + } +} + +static void sendend_switch_change(struct work_struct *ignored) +{ + struct sec_gpio_info *det_jack = &hi->port.det_jack; + struct sec_gpio_info *send_end = &hi->port.send_end; + int state, headset_state; + + + SEC_JACKDEV_DBG(""); + + del_timer(&send_end_key_event_timer); + send_end_key_timer_token = 0; + + headset_state = gpio_get_value(det_jack->gpio) ^ det_jack->low_active; + state = gpio_get_value(send_end->gpio) ^ send_end->low_active; + + if(headset_state && send_end_irq_token) //headset connect && send irq enable + { + if(!state) + { + printk("SEND/END key is released\n"); + switch_set_state(&switch_sendend, 0); + input_report_key(hi->input, KEYCODE_SENDEND, 0); + input_sync(hi->input); + hi->send_end_key_pressed = 0; + } + else + { + /* prevent suspend to allow user space to respond to switch */ + wake_lock_timeout(&jack_sendend_wake_lock, WAKE_LOCK_TIME); + send_end_key_event_timer.expires = SEND_END_CHECK_TIME; + add_timer(&send_end_key_event_timer); + switch_set_state(&switch_sendend, 1); + SEC_JACKDEV_DBG("SEND/END key is pressed : timer start\n"); + } + + } + else + { + SEC_JACKDEV_DBG("SEND/END Button is %s but headset disconnect or irq disable.\n", state?"pressed":"released"); + } +} + +static DECLARE_WORK(jack_detect_work, jack_detect_change); +static DECLARE_WORK(sendend_switch_work, sendend_switch_change); + +//IRQ Handler +static irqreturn_t detect_irq_handler(int irq, void *dev_id) +{ + SEC_JACKDEV_DBG("jack isr"); + schedule_work(&jack_detect_work); + return IRQ_HANDLED; +} + +static void jack_detect_timer_handler(unsigned long arg) +{ + struct sec_gpio_info *det_jack = &hi->port.det_jack; + int state; + + state = gpio_get_value(det_jack->gpio) ^ det_jack->low_active; + + if(state) + { + SEC_JACKDEV_DBG("jack_detect_timer_token is %d\n", jack_detect_timer_token); + if(jack_detect_timer_token < DETECTION_CHECK_COUNT) + { + jack_detect_timer.expires = DETECTION_CHECK_TIME; + add_timer(&jack_detect_timer); + jack_detect_timer_token++; + } + else if(jack_detect_timer_token == DETECTION_CHECK_COUNT) + { + jack_detect_timer.expires = SEND_END_ENABLE_TIME; + + printk("EAR_MICBIAS On\n"); + gpio_set_value(GPIO_EAR_MICBIAS0_EN, 1); + gpio_set_value(GPIO_EAR_MICBIAS_EN, 1); + + jack_detect_timer_token = 0; + schedule_delayed_work(&detect_jack_type_work,50); + } + else if(jack_detect_timer_token == 4) + { + SEC_JACKDEV_DBG("mic bias enable add work queue \n"); + jack_detect_timer_token = 0; + } + else + { + printk(KERN_ALERT "wrong jack_detect_timer_token count %d", jack_detect_timer_token); + } + } + else + { + printk(KERN_ALERT "headset detach!! %d", jack_detect_timer_token); + } +} + + +static void send_end_key_event_timer_handler(unsigned long arg) +{ + struct sec_gpio_info *det_jack = &hi->port.det_jack; + struct sec_gpio_info *send_end = &hi->port.send_end; + int sendend_state, headset_state = 0; + + headset_state = gpio_get_value(det_jack->gpio) ^ det_jack->low_active; + sendend_state = gpio_get_value(send_end->gpio) ^ send_end->low_active; + + if(headset_state && sendend_state) + { + if(send_end_key_timer_token < SEND_END_CHECK_COUNT) + { + send_end_key_timer_token++; + send_end_key_event_timer.expires = SEND_END_CHECK_TIME; + add_timer(&send_end_key_event_timer); + SEC_JACKDEV_DBG("SEND/END key pressed Timer, Restart %d", send_end_key_timer_token); + } + else if(send_end_key_timer_token == SEND_END_CHECK_COUNT) + { + printk("SEND/END key is pressed\n"); + input_report_key(hi->input, KEYCODE_SENDEND, 1); + input_sync(hi->input); + hi->send_end_key_pressed = 1; + send_end_key_timer_token = 0; + } + else + { + printk(KERN_ALERT "[JACK]wrong timer counter %d\n", send_end_key_timer_token); + } + } + else + { + printk(KERN_ALERT "[JACK]GPIO Error\n"); + } +} + +static irqreturn_t send_end_irq_handler(int irq, void *dev_id) +{ + struct sec_gpio_info *det_jack = &hi->port.det_jack; + int headset_state; + + SEC_JACKDEV_DBG("sendend isr"); + del_timer(&send_end_key_event_timer); + headset_state = gpio_get_value(det_jack->gpio) ^ det_jack->low_active; + + if (headset_state) + { + schedule_work(&sendend_switch_work); + } + + return IRQ_HANDLED; +} + +//USER can select jack type if driver can't check the jack type +static int strtoi(const char *buf) +{ + int ret; + ret = buf[0]-48; + return ret; +} + +static ssize_t select_jack_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + printk(KERN_INFO "[JACK] %s : operate nothing\n", __FUNCTION__); + + return 0; +} + +static ssize_t select_jack_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) +{ + int value = 0; + struct sec_gpio_info *det_jack = &hi->port.det_jack; + struct sec_gpio_info *send_end = &hi->port.send_end; + int state = gpio_get_value(det_jack->gpio) ^ det_jack->low_active; + + SEC_JACKDEV_DBG("buf = %s", buf); + SEC_JACKDEV_DBG("buf size = %d", sizeof(buf)); + SEC_JACKDEV_DBG("buf size = %d", strlen(buf)); + + if(state) + { + if(current_jack_type_status != SEC_UNKNOWN_DEVICE) + { + printk(KERN_ERR "user can't select jack device if current_jack_status isn't unknown status"); + return -1; + } + + if(sizeof(buf)!=1) + { + printk("input error\n"); + printk("Must be stored ( 1,2,4)\n"); + return -1; + } + + value = strtoi(buf); + SEC_JACKDEV_DBG("User selection : 0X%x", value); + + switch(value) + { + case SEC_HEADSET_3_POLE_DEVICE: + { + current_jack_type_status = SEC_HEADSET_3_POLE_DEVICE; + switch_set_state(&switch_jack_detection, current_jack_type_status); + break; + } + case SEC_HEADSET_4_POLE_DEVICE: + { + enable_irq (send_end->eint); + enable_irq_wake (send_end->eint); + + send_end_irq_token++; + current_jack_type_status = SEC_HEADSET_4_POLE_DEVICE; + switch_set_state(&switch_jack_detection, current_jack_type_status); + break; + } + case SEC_TVOUT_DEVICE: + { + current_jack_type_status = SEC_TVOUT_DEVICE; + + printk("EAR_MICBIAS Off\n"); + gpio_set_value(GPIO_EAR_MICBIAS0_EN, 0); + gpio_set_value(GPIO_EAR_MICBIAS_EN, 0); + + switch_set_state(&switch_jack_detection, current_jack_type_status); + break; + } + } + } + else + { + printk(KERN_ALERT "Error : mic bias enable complete but headset detached!!\n"); + current_jack_type_status = SEC_JACK_NO_DEVICE; + + printk("EAR_MICBIAS Off\n"); + gpio_set_value(GPIO_EAR_MICBIAS0_EN, 0); + gpio_set_value(GPIO_EAR_MICBIAS_EN, 0); + } + + return size; +} + +static DEVICE_ATTR(select_jack, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH, select_jack_show, select_jack_store); + +static int sec_jack_probe(struct platform_device *pdev) +{ + int ret; + struct sec_jack_platform_data *pdata = pdev->dev.platform_data; + struct sec_gpio_info *det_jack; + struct sec_gpio_info *send_end; + struct input_dev *input; + current_jack_type_status = SEC_JACK_NO_DEVICE; + + printk(KERN_INFO "SEC JACK: Registering jack driver\n"); + + hi = kzalloc(sizeof(struct sec_jack_info), GFP_KERNEL); + if (!hi) + return -ENOMEM; + + memcpy (&hi->port, pdata->port, sizeof(struct sec_jack_port)); + + input = hi->input = input_allocate_device(); + if (!input) + { + ret = -ENOMEM; + printk(KERN_ERR "SEC JACK: Failed to allocate input device.\n"); + goto err_request_input_dev; + } + + input->name = "sec_jack"; + set_bit(EV_SYN, input->evbit); + set_bit(EV_KEY, input->evbit); + set_bit(KEYCODE_SENDEND, input->keybit); + + ret = input_register_device(input); + if (ret < 0) + { + printk(KERN_ERR "SEC JACK: Failed to register driver\n"); + goto err_register_input_dev; + } + + init_timer(&jack_detect_timer); + jack_detect_timer.function = jack_detect_timer_handler; + + init_timer(&send_end_key_event_timer); + send_end_key_event_timer.function = send_end_key_event_timer_handler; + + SEC_JACKDEV_DBG("registering switch_sendend switch_dev sysfs sec_jack"); + + ret = switch_dev_register(&switch_jack_detection); + if (ret < 0) + { + printk(KERN_ERR "SEC JACK: Failed to register switch device\n"); + goto err_switch_dev_register; + } + + ret = switch_dev_register(&switch_sendend); + if (ret < 0) + { + printk(KERN_ERR "SEC JACK: Failed to register switch sendend device\n"); + goto err_switch_dev_register; + } + + //Create JACK Device file in Sysfs + jack_class = class_create(THIS_MODULE, "jack"); + if(IS_ERR(jack_class)) + { + printk(KERN_ERR "Failed to create class(sec_jack)\n"); + } + + jack_selector_fs = device_create(jack_class, NULL, 0, NULL, "jack_selector"); + if (IS_ERR(jack_selector_fs)) + printk(KERN_ERR "Failed to create device(sec_jack)!= %ld\n", IS_ERR(jack_selector_fs)); + + if (device_create_file(jack_selector_fs, &dev_attr_select_jack) < 0) + printk(KERN_ERR "Failed to create device file(%s)!\n", dev_attr_select_jack.attr.name); + + //GPIO configuration + send_end = &hi->port.send_end; + s3c_gpio_cfgpin(send_end->gpio, S3C_GPIO_SFN(send_end->gpio_af)); + s3c_gpio_setpull(send_end->gpio, S3C_GPIO_PULL_NONE); + irq_set_irq_type(send_end->eint, IRQ_TYPE_EDGE_BOTH); + + ret = request_irq(send_end->eint, send_end_irq_handler, IRQF_DISABLED, "sec_headset_send_end", NULL); + + SEC_JACKDEV_DBG("sended isr send=0X%x, ret =%d", send_end->eint, ret); + if (ret < 0) + { + printk(KERN_ERR "SEC HEADSET: Failed to register send/end interrupt.\n"); + det_jack = &hi->port.det_jack; + goto err_request_send_end_irq; + } + + enable_irq_wake(send_end->eint); //Enables and disables must match + + disable_irq(send_end->eint); + disable_irq_wake(send_end->eint); + + det_jack = &hi->port.det_jack; + s3c_gpio_cfgpin(det_jack->gpio, S3C_GPIO_SFN(det_jack->gpio_af)); + s3c_gpio_setpull(det_jack->gpio, S3C_GPIO_PULL_NONE); + irq_set_irq_type(det_jack->eint, IRQ_TYPE_EDGE_BOTH); + + ret = request_irq(det_jack->eint, detect_irq_handler, IRQF_DISABLED, "sec_headset_detect", NULL); + + SEC_JACKDEV_DBG("det isr det=0X%x, ret =%d", det_jack->eint, ret); + if (ret < 0) + { + printk(KERN_ERR "SEC HEADSET: Failed to register detect interrupt.\n"); + goto err_request_detect_irq; + } + + enable_irq_wake(det_jack->eint); + + wake_lock_init(&jack_sendend_wake_lock, WAKE_LOCK_SUSPEND, "sec_jack"); + + + if (gpio_is_valid(GPIO_EAR_MICBIAS0_EN)) { + if (gpio_request(GPIO_EAR_MICBIAS0_EN, "MP05")) + printk(KERN_ERR "Failed to request GPIO_EAR_MICBIAS0_EN! \n"); + gpio_direction_output(GPIO_EAR_MICBIAS0_EN, 0); + } + s3c_gpio_setpull(GPIO_EAR_MICBIAS0_EN, S3C_GPIO_PULL_NONE); + + s3c_gpio_slp_cfgpin(GPIO_EAR_MICBIAS0_EN, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_EAR_MICBIAS0_EN, S3C_GPIO_PULL_NONE); + + + if (gpio_is_valid(GPIO_EAR_MICBIAS_EN)) { + if (gpio_request(GPIO_EAR_MICBIAS_EN, "MP01")) + printk(KERN_ERR "Failed to request GPIO_EAR_MICBIAS_EN! \n"); + gpio_direction_output(GPIO_EAR_MICBIAS_EN, 0); + } + s3c_gpio_setpull(GPIO_EAR_MICBIAS_EN, S3C_GPIO_PULL_NONE); + + s3c_gpio_slp_cfgpin(GPIO_EAR_MICBIAS_EN, S3C_GPIO_SLP_PREV); + s3c_gpio_slp_setpull_updown(GPIO_EAR_MICBIAS_EN, S3C_GPIO_PULL_NONE); + + printk("EAR_MICBIAS Init\n"); + + schedule_work(&jack_detect_work); + + return 0; + +err_request_send_end_irq: + free_irq(det_jack->eint, 0); +err_request_detect_irq: + switch_dev_unregister(&switch_jack_detection); +err_switch_dev_register: + input_unregister_device(input); +err_register_input_dev: + input_free_device(input); +err_request_input_dev: + kfree (hi); + + return ret; +} + +static int sec_jack_remove(struct platform_device *pdev) +{ + SEC_JACKDEV_DBG(""); + input_unregister_device(hi->input); + free_irq(hi->port.det_jack.eint, 0); + free_irq(hi->port.send_end.eint, 0); + switch_dev_unregister(&switch_jack_detection); + return 0; +} + +#ifdef CONFIG_PM +static int sec_jack_suspend(struct platform_device *pdev, pm_message_t state) +{ + SEC_JACKDEV_DBG(""); + flush_scheduled_work(); + return 0; +} +static int sec_jack_resume(struct platform_device *pdev) +{ + SEC_JACKDEV_DBG(""); + schedule_work(&jack_detect_work); + schedule_work(&sendend_switch_work); + return 0; +} +#else +#define s3c_headset_resume NULL +#define s3c_headset_suspend NULL +#endif + +static int __init sec_jack_init(void) +{ + SEC_JACKDEV_DBG(""); + return platform_driver_register(&sec_jack_driver); +} + +static void __exit sec_jack_exit(void) +{ + platform_driver_unregister(&sec_jack_driver); +} + +static struct platform_driver sec_jack_driver = { + .probe = sec_jack_probe, + .remove = sec_jack_remove, + .suspend = sec_jack_suspend, + .resume = sec_jack_resume, + .driver = { + .name = "sec_jack", + .owner = THIS_MODULE, + }, +}; + +module_init(sec_jack_init); +module_exit(sec_jack_exit); + +MODULE_AUTHOR("Uk Kim <w0806.kim@samsung.com>"); +MODULE_DESCRIPTION("SEC JACK detection driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-s5pv210/setup-fb.c b/arch/arm/mach-s5pv210/setup-fb.c index 85adf23..2663549 100644 --- a/arch/arm/mach-s5pv210/setup-fb.c +++ b/arch/arm/mach-s5pv210/setup-fb.c @@ -73,7 +73,11 @@ int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk) goto err_clk1; } +#if defined(CONFIG_S5PV210_SCLKFIMD_USE_VPLL) + mout_mpll = clk_get(&pdev->dev, "sclk_vpll"); +#else mout_mpll = clk_get(&pdev->dev, "mout_mpll"); +#endif if (IS_ERR(mout_mpll)) { dev_err(&pdev->dev, "failed to get mout_mpll\n"); goto err_clk2; @@ -84,9 +88,64 @@ int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk) if (!rate) rate = 166750000; +#if defined(CONFIG_FB_S3C_LVDS) + #if defined(CONFIG_TARGET_PCLK_44_46) + rate = 45000000; + #elif defined(CONFIG_TARGET_PCLK_47_6) + //P1_ATT PCLK -> 47.6MHz + rate = 48000000; + #else + rate = 54000000; + #endif +#endif + clk_set_rate(sclk, rate); dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate); +#if defined(CONFIG_FB_S3C_MDNIE) && defined(CONFIG_FB_S3C_LVDS) + { + struct clk * clk_xusb; + struct clk * sclk_mdnie; + struct clk * sclk_mdnie_pwm; + sclk_mdnie = clk_get(&pdev->dev, "sclk_mdnie"); + if (IS_ERR(sclk_mdnie)) { + dev_err(&pdev->dev, "failed to get sclk for mdnie\n"); + } + else + { + clk_set_parent(sclk_mdnie, mout_mpll); + + #if defined(CONFIG_TARGET_PCLK_44_46) + clk_set_rate(sclk_mdnie, 45*1000000); + #elif defined(CONFIG_TARGET_PCLK_47_6) + //P1_ATT PCLK -> 47.6MHz + clk_set_rate(sclk_mdnie, 48*1000000); + #else + clk_set_rate(sclk_mdnie, 54*1000000); + #endif + clk_put(sclk_mdnie); + } + sclk_mdnie_pwm = clk_get(&pdev->dev, "sclk_mdnie_pwm"); + if (IS_ERR(sclk_mdnie_pwm)) { + dev_err(&pdev->dev, "failed to get sclk for mdnie pwm\n"); + } + else + { + clk_xusb = clk_get(&pdev->dev, "xusbxti"); + if (IS_ERR(clk_xusb)) { + dev_err(&pdev->dev, "failed to get xusbxti for mdnie pwm\n"); + } + else + { + clk_set_parent(sclk_mdnie_pwm, clk_xusb); + clk_put(clk_xusb); + } + clk_set_rate(sclk_mdnie_pwm, 2400*1000); // mdnie pwm need to 24Khz*100 + clk_put(sclk_mdnie_pwm); + } + } +#endif + clk_put(mout_mpll); clk_enable(sclk); diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index 26aaa87..ecf58a9 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c @@ -61,7 +61,7 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) printk(KERN_ERR "Wrong SD/MMC bus width : %d\n", width); } - if (machine_is_herring() || machine_is_aries()) { + if (machine_is_herring() || machine_is_aries() || machine_is_p1()) { s3c_gpio_cfgpin(S5PV210_GPJ2(7), S3C_GPIO_OUTPUT); s3c_gpio_setpull(S5PV210_GPJ2(7), S3C_GPIO_PULL_NONE); gpio_set_value(S5PV210_GPJ2(7), 1); @@ -71,6 +71,7 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) gpio_direction_output(S5PV210_GPJ2(7), 1); s3c_gpio_setpull(S5PV210_GPJ2(7), S3C_GPIO_PULL_NONE); } + } void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c index d778239..a209719 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ b/arch/arm/mach-s5pv210/setup-sdhci.c @@ -28,6 +28,12 @@ #include <mach/regs-gpio.h> #include <mach/gpio.h> +#ifdef CONFIG_MACH_P1 +#include <mach/gpio-p1.h> +#include <linux/regulator/consumer.h> +#include <linux/err.h> +#endif + #include "herring.h" /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ @@ -82,8 +88,8 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, if ((ios->clock > range_start) && (ios->clock < range_end)) ctrl3 = S3C_SDHCI_CTRL3_FCSELTX_BASIC | S3C_SDHCI_CTRL3_FCSELRX_BASIC; - else if (machine_is_herring() && herring_is_cdma_wimax_dev() && - dev->id == 2) { + else if (((machine_is_herring() && herring_is_cdma_wimax_dev()) || + machine_is_p1()) && dev->id == 2) { ctrl3 = S3C_SDHCI_CTRL3_FCSELTX_BASIC; //if(card->type & MMC_TYPE_SDIO) ctrl3 |= S3C_SDHCI_CTRL3_FCSELRX_BASIC; @@ -148,11 +154,79 @@ void universal_sdhci2_cfg_ext_cd(void) #if defined(CONFIG_SAMSUNG_CAPTIVATE) || defined(CONFIG_SAMSUNG_VIBRANT) s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_UP); #else +#if defined(CONFIG_PHONE_P1_GSM) + s3c_gpio_cfgpin(GPIO_T_FLASH_DETECT, S3C_GPIO_SFN(GPIO_T_FLASH_DETECT_AF)); +#elif defined(CONFIG_PHONE_P1_CDMA) + s3c_gpio_cfgpin(S5PV210_GPH3(4),S3C_GPIO_SFN(0xf)); +#endif s3c_gpio_setpull(S5PV210_GPH3(4), S3C_GPIO_PULL_NONE); #endif irq_set_irq_type(IRQ_EINT(28), IRQ_TYPE_EDGE_BOTH); } +#ifdef CONFIG_MACH_P1 +static unsigned int vreg_sts = 0; +void s5pv210_sdhci0_translate_vdd(struct platform_device *pdev, + unsigned int vdd) +{ + unsigned int flag = 0; + + if (pdev->id != 0) /* MoviNAND */ + return; + + flag = 1 << pdev->id; + + if (vdd == 0) { + if (vreg_sts & flag) { + gpio_set_value(GPIO_MASSMEMORY_EN, GPIO_LEVEL_LOW); + printk(KERN_DEBUG "%s.%d: ldo down\n", pdev->name, pdev->id); + vreg_sts &= ~flag; + } + } + else { + if (!(vreg_sts & flag)) { + gpio_set_value(GPIO_MASSMEMORY_EN, GPIO_LEVEL_HIGH); + printk(KERN_DEBUG "%s.%d: ldo on\n", pdev->name, pdev->id); + vreg_sts |= flag; + } + } +} + +void s5pv210_sdhci2_translate_vdd(struct platform_device *pdev, unsigned int vdd) +{ + unsigned int flag = 0; + struct regulator *vcc_vtf; + + if (pdev->id != 2) /* T-FLSH */ + return; + + flag = 1 << pdev->id; + + vcc_vtf = regulator_get(NULL, "vcc_vtf"); + if (IS_ERR_OR_NULL(vcc_vtf)) { + pr_err("failed to get T-Flash regulator"); + return; + } + + if (vdd == 0) { + if (vreg_sts & flag) { + printk(KERN_DEBUG "%s.%d: ldo down\n", pdev->name, pdev->id); + regulator_disable(vcc_vtf); + vreg_sts &= ~flag; + } + } + else { + if (!(vreg_sts & flag)) { + printk(KERN_DEBUG "%s.%d: ldo on\n", pdev->name, pdev->id); + regulator_enable(vcc_vtf); + vreg_sts |= flag; + } + } + + regulator_put(vcc_vtf); +} +#endif + static struct s3c_sdhci_platdata hsmmc0_platdata = { #if defined(CONFIG_S5PV210_SD_CH0_8BIT) .max_width = 8, @@ -170,6 +244,9 @@ static struct s3c_sdhci_platdata hsmmc2_platdata = { .max_width = 8, .host_caps = MMC_CAP_8_BIT_DATA, #endif +#ifdef CONFIG_MACH_P1 + .translate_vdd = s5pv210_sdhci2_translate_vdd, +#endif }; #endif @@ -242,18 +319,21 @@ EXPORT_SYMBOL_GPL(sdhci_s3c_force_presence_change); void s3c_sdhci_set_platdata(void) { #if defined(CONFIG_S3C_DEV_HSMMC) - if (machine_is_herring() || machine_is_aries()) { /* TODO: move to mach-herring.c */ + if (machine_is_herring() || machine_is_aries() || machine_is_p1()) { + /* TODO: move to mach-herring.c */ hsmmc0_platdata.cd_type = S3C_SDHCI_CD_PERMANENT; } + s3c_sdhci0_set_platdata(&hsmmc0_platdata); #endif #if defined(CONFIG_S3C_DEV_HSMMC1) - if (machine_is_aries()) { + if (machine_is_aries() || machine_is_p1()) { hsmmc1_platdata.cd_type = S3C_SDHCI_CD_EXTERNAL; hsmmc1_platdata.ext_cd_init = ext_cd_init_hsmmc1; hsmmc1_platdata.ext_cd_cleanup = ext_cd_cleanup_hsmmc1; hsmmc1_platdata.built_in = 1; } + s3c_sdhci1_set_platdata(&hsmmc1_platdata); #endif #if defined(CONFIG_S3C_DEV_HSMMC2) @@ -273,7 +353,7 @@ void s3c_sdhci_set_platdata(void) } } - if (machine_is_aries()) { + if (machine_is_aries() || machine_is_p1()) { hsmmc2_platdata.cd_type = S3C_SDHCI_CD_GPIO; hsmmc2_platdata.ext_cd_gpio = S5PV210_GPH3(4); hsmmc2_platdata.ext_cd_gpio_invert = true; @@ -283,12 +363,13 @@ void s3c_sdhci_set_platdata(void) s3c_sdhci2_set_platdata(&hsmmc2_platdata); #endif #if defined(CONFIG_S3C_DEV_HSMMC3) - if (machine_is_herring() || machine_is_aries()) { + if (machine_is_herring() || machine_is_aries() || machine_is_p1()) { hsmmc3_platdata.cd_type = S3C_SDHCI_CD_EXTERNAL; hsmmc3_platdata.ext_cd_init = ext_cd_init_hsmmc3; hsmmc3_platdata.ext_cd_cleanup = ext_cd_cleanup_hsmmc3; hsmmc3_platdata.built_in = 1; } + s3c_sdhci3_set_platdata(&hsmmc3_platdata); #endif }; diff --git a/arch/arm/plat-s5p/devs.c b/arch/arm/plat-s5p/devs.c index f961d66..03335b6 100644 --- a/arch/arm/plat-s5p/devs.c +++ b/arch/arm/plat-s5p/devs.c @@ -649,3 +649,35 @@ struct platform_device s3c_device_usbgadget = { }; #endif +#if defined(CONFIG_VIDEO_TSI) + +/*TSI Interface*/ +static u64 tsi_dma_mask = 0xffffffffUL; + +static struct resource s3c_tsi_resource[] = { + [0] = { + .start = S5P_PA_TSI, + .end = S5P_PA_TSI + S5P_SZ_TSI - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TSI, + .end = IRQ_TSI, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s3c_device_tsi = { + .name = "s3c-tsi", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_tsi_resource), + .resource = s3c_tsi_resource, + .dev = { + .dma_mask = &tsi_dma_mask, + .coherent_dma_mask = 0xffffffffUL + } + + +}; +EXPORT_SYMBOL(s3c_device_tsi); +#endif diff --git a/arch/arm/plat-s5p/hr-time-rtc.c b/arch/arm/plat-s5p/hr-time-rtc.c index 9dfc727..6746b49 100644 --- a/arch/arm/plat-s5p/hr-time-rtc.c +++ b/arch/arm/plat-s5p/hr-time-rtc.c @@ -431,7 +431,10 @@ unsigned long long sched_clock(void) static void s5p_timer_setup(void) { unsigned long rate; + +#ifdef CONFIG_MACH_ARIES unsigned int tmp; +#endif /* Setup event timer using XrtcXTI */ if (clk_event == NULL) @@ -442,11 +445,13 @@ static void s5p_timer_setup(void) rate = clk_get_rate(clk_event); +#ifdef CONFIG_MACH_ARIES tmp = readl(rtc_base + S3C2410_RTCCON) & ~(S3C_RTCCON_TICEN); /* We only support 32768 Hz : [7:4] = 0x0 */ writel(tmp & ~0xf0, rtc_base + S3C2410_RTCCON); +#endif s5p_init_dynamic_tick_timer(rate); diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c index 9296bd8..489cf64 100644 --- a/arch/arm/plat-samsung/dev-hsmmc.c +++ b/arch/arm/plat-samsung/dev-hsmmc.c @@ -82,4 +82,8 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) set->must_maintain_clock = pd->must_maintain_clock; if (pd->enable_intr_on_resume) set->enable_intr_on_resume = pd->enable_intr_on_resume; +#ifdef CONFIG_MACH_P1 + if (pd->translate_vdd) + set->translate_vdd = pd->translate_vdd; +#endif } diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c index 4e7b100..024de9b 100644 --- a/arch/arm/plat-samsung/dev-hsmmc1.c +++ b/arch/arm/plat-samsung/dev-hsmmc1.c @@ -82,4 +82,8 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) set->must_maintain_clock = pd->must_maintain_clock; if (pd->enable_intr_on_resume) set->enable_intr_on_resume = pd->enable_intr_on_resume; +#ifdef CONFIG_MACH_P1 + if (pd->translate_vdd) + set->translate_vdd = pd->translate_vdd; +#endif } diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c index ef2e8c6..61f7b30 100644 --- a/arch/arm/plat-samsung/dev-hsmmc2.c +++ b/arch/arm/plat-samsung/dev-hsmmc2.c @@ -83,4 +83,8 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) set->must_maintain_clock = pd->must_maintain_clock; if (pd->enable_intr_on_resume) set->enable_intr_on_resume = pd->enable_intr_on_resume; +#ifdef CONFIG_MACH_P1 + if (pd->translate_vdd) + set->translate_vdd = pd->translate_vdd; +#endif } diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c index da729c5..4eb4461 100644 --- a/arch/arm/plat-samsung/dev-hsmmc3.c +++ b/arch/arm/plat-samsung/dev-hsmmc3.c @@ -86,4 +86,8 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd) set->must_maintain_clock = pd->must_maintain_clock; if (pd->enable_intr_on_resume) set->enable_intr_on_resume = pd->enable_intr_on_resume; +#ifdef CONFIG_MACH_P1 + if (pd->translate_vdd) + set->translate_vdd = pd->translate_vdd; +#endif } diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 54e0b6e..020a315 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -119,6 +119,11 @@ extern struct platform_device s5p_device_rotator; extern struct platform_device s5p_device_tvout; extern struct platform_device s5p_device_g3d; +#ifdef CONFIG_MACH_P1 +extern struct platform_device s5p_device_cec; +extern struct platform_device s5p_device_hpd; +#endif + extern struct platform_device s5pv210_device_ac97; extern struct platform_device s5pv210_device_pcm0; extern struct platform_device s5pv210_device_pcm1; @@ -198,4 +203,8 @@ extern struct platform_device s3c_device_ac97; extern void *s3c_set_platdata(void *pd, size_t pdsize, struct platform_device *pdev); +#if defined(CONFIG_VIDEO_TSI) +extern struct platform_device s3c_device_tsi; +#endif + #endif /* __PLAT_DEVS_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 0c386fc..0ec16a5 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -88,6 +88,10 @@ struct s3c_sdhci_platdata { int rx_cfg; int tx_cfg; +#ifdef CONFIG_MACH_P1 + void (*translate_vdd)(struct platform_device *pdev, unsigned int vdd); +#endif + /* add to deal with non-removable device */ int built_in; diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index 8494c87..023e158 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -56,14 +56,19 @@ struct pmstats { static struct pmstats *pmstats; static struct pmstats *pmstats_last; +#ifdef CONFIG_MACH_ARIES +#define PMSTATS_LEN 4096 +#else // CONFIG_MACH_P1 +#define PMSTATS_LEN sizeof(struct pmstats) +#endif static ssize_t pmstats_read(struct file *file, char __user *buf, size_t len, loff_t *offset) { if (*offset != 0) return 0; - if (len > 4096) - len = 4096; + if (len > PMSTATS_LEN) + len = PMSTATS_LEN; if (copy_to_user(buf, file->private_data, len)) return -EFAULT; @@ -88,17 +93,17 @@ void __init pmstats_init(void) { pr_info("pmstats at %08x\n", pm_debug_scratchpad); if (pm_debug_scratchpad) - pmstats = ioremap(pm_debug_scratchpad, 4096); + pmstats = ioremap(pm_debug_scratchpad, PMSTATS_LEN); else - pmstats = kzalloc(4096, GFP_ATOMIC); + pmstats = kzalloc(PMSTATS_LEN, GFP_ATOMIC); if (!memcmp(pmstats->magic, PMSTATS_MAGIC, 16)) { - pmstats_last = kzalloc(4096, GFP_ATOMIC); + pmstats_last = kzalloc(PMSTATS_LEN, GFP_ATOMIC); if (pmstats_last) - memcpy(pmstats_last, pmstats, 4096); + memcpy(pmstats_last, pmstats, PMSTATS_LEN); } - memset(pmstats, 0, 4096); + memset(pmstats, 0, PMSTATS_LEN); memcpy(pmstats->magic, PMSTATS_MAGIC, 16); debugfs_create_file("pmstats", 0444, NULL, pmstats, &pmstats_ops); diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 11eaf19..d30a9a9 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1113,4 +1113,5 @@ blissc MACH_BLISSC BLISSC 3491 thales_adc MACH_THALES_ADC THALES_ADC 3492 ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493 atdgp318 MACH_ATDGP318 ATDGP318 3494 +p1 MACH_P1 P1 9998 aries MACH_ARIES ARIES 9999
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