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| author | Mike Frysinger <vapier@gentoo.org> | 2010-06-09 03:02:09 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-06 12:55:49 -0400 |
| commit | 502c8a0e07450ff886b80a11150a123bae92f3f7 (patch) | |
| tree | 23cb5a47714e4f863035edfbde5c712dd820d314 /arch/blackfin | |
| parent | 306208f40cde5f835e891976031571b81815b9df (diff) | |
| download | kernel_samsung_aries-502c8a0e07450ff886b80a11150a123bae92f3f7.zip kernel_samsung_aries-502c8a0e07450ff886b80a11150a123bae92f3f7.tar.gz kernel_samsung_aries-502c8a0e07450ff886b80a11150a123bae92f3f7.tar.bz2 | |
Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin)
Even though the PH8 pin is only internal to the processor packaging, it
can be controlled like any other GPIO pin. Now that we have a proper GPIO
define, we can fix the SPI0 CS4 define for the internal SPI flash.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/gpio.h | 3 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/portmux.h | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h index bbab2d7..3532a74 100644 --- a/arch/blackfin/mach-bf518/include/mach/gpio.h +++ b/arch/blackfin/mach-bf518/include/mach/gpio.h @@ -7,7 +7,7 @@ #ifndef _MACH_GPIO_H_ #define _MACH_GPIO_H_ -#define MAX_BLACKFIN_GPIOS 40 +#define MAX_BLACKFIN_GPIOS 41 #define GPIO_PF0 0 #define GPIO_PF1 1 @@ -49,6 +49,7 @@ #define GPIO_PH5 37 #define GPIO_PH6 38 #define GPIO_PH7 39 +#define GPIO_PH8 40 #define PORT_F GPIO_PF0 #define PORT_G GPIO_PG0 diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h index d39eb4b..5d62430 100644 --- a/arch/blackfin/mach-bf518/include/mach/portmux.h +++ b/arch/blackfin/mach-bf518/include/mach/portmux.h @@ -95,7 +95,7 @@ #define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) -#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2)) #define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) #define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) |