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| author | Graf Yang <graf.yang@analog.com> | 2009-07-10 11:34:51 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-07-16 01:52:51 -0400 |
| commit | 5bc6e3cfe6db5f33c60f042a9ba203431f334756 (patch) | |
| tree | ff171234a9d19171e955bc1d05279e38c4b39f97 /arch/blackfin | |
| parent | f574a76a3b19848ac61814756716e26f85f2c3f7 (diff) | |
| download | kernel_samsung_aries-5bc6e3cfe6db5f33c60f042a9ba203431f334756.zip kernel_samsung_aries-5bc6e3cfe6db5f33c60f042a9ba203431f334756.tar.gz kernel_samsung_aries-5bc6e3cfe6db5f33c60f042a9ba203431f334756.tar.bz2 | |
Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions. Any code that attempted to use these would wrongly crash due to
a CPLB miss.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
| -rw-r--r-- | arch/blackfin/kernel/cplb-nompu/cplbinit.c | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index d6c0677..685f160 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) } /* Cover L1 memory. One 4M area for code and data each is enough. */ - if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { - d_tbl[i_d].addr = L1_DATA_A_START; - d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; + if (cpu == 0) { + if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { + d_tbl[i_d].addr = L1_DATA_A_START; + d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; + } + i_tbl[i_i].addr = L1_CODE_START; + i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; } - i_tbl[i_i].addr = L1_CODE_START; - i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; - +#ifdef CONFIG_SMP + else { + if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { + d_tbl[i_d].addr = COREB_L1_DATA_A_START; + d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; + } + i_tbl[i_i].addr = COREB_L1_CODE_START; + i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; + } +#endif first_switched_dcplb = i_d; first_switched_icplb = i_i; |