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authorDavid Daney <ddaney@caviumnetworks.com>2010-02-10 15:12:48 -0800
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 12:53:26 +0100
commit6f329468f3086e9d8f3832930fdb09ab3769176b (patch)
treed77b274399cf101fba59b0de01fd9491b4e28fee /arch/mips/include
parent6dd9344cfc41bcc60a01cdc828cb278be7a10e01 (diff)
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MIPS: Give Octeon+ CPUs their own cputype.
This allows us to treat them differently at runtime. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index cf373a9..a5acda4 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -224,7 +224,7 @@ enum cpu_type_enum {
* MIPS64 class processors
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
- CPU_CAVIUM_OCTEON,
+ CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
CPU_LAST
};