aboutsummaryrefslogtreecommitdiffstats
path: root/arch/parisc/kernel
diff options
context:
space:
mode:
authorGrant Grundler <grundler@parisc-linux.org>2005-10-21 22:55:51 -0400
committerKyle McMartin <kyle@parisc-linux.org>2005-10-21 22:55:51 -0400
commit9b3b331d0322b60de1bde20528bf974f62804ffa (patch)
tree6c9f07131f4985f8b48ccd198a88d6405fc43869 /arch/parisc/kernel
parent37318a3cb1028933417533084ddbf9d84be06878 (diff)
downloadkernel_samsung_aries-9b3b331d0322b60de1bde20528bf974f62804ffa.zip
kernel_samsung_aries-9b3b331d0322b60de1bde20528bf974f62804ffa.tar.gz
kernel_samsung_aries-9b3b331d0322b60de1bde20528bf974f62804ffa.tar.bz2
[PARISC] Properly specify index field to I/D cache flush ops
replace use of "0" with "%r0" since PA 1.1 I/D flush ops only take a general register and not an immediate value for the index field. This just forces the code to always be PA 1.1 "clean". From: Joel Soete <soete.joel@tiscali.be> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch/parisc/kernel')
-rw-r--r--arch/parisc/kernel/pacache.S4
-rw-r--r--arch/parisc/kernel/signal.c11
2 files changed, 9 insertions, 6 deletions
diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S
index e217ae3..08cde5a 100644
--- a/arch/parisc/kernel/pacache.S
+++ b/arch/parisc/kernel/pacache.S
@@ -227,7 +227,7 @@ flush_instruction_cache_local:
fimanyloop: /* Loop if LOOP >= 2 */
ADDIB> -1, %r31, fimanyloop /* Adjusted inner loop decr */
- fice 0(%sr1, %arg0)
+ fice %r0(%sr1, %arg0)
fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
ADDIB<=,n -1, %arg2, fisync /* Outer loop decr */
@@ -269,7 +269,7 @@ flush_data_cache_local:
fdmanyloop: /* Loop if LOOP >= 2 */
ADDIB> -1, %r31, fdmanyloop /* Adjusted inner loop decr */
- fdce 0(%sr1, %arg0)
+ fdce %r0(%sr1, %arg0)
fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */
movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
ADDIB<=,n -1, %arg2, fdsync /* Outer loop decr */
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index befdfe7..82c24e6 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -625,11 +625,14 @@ do_signal(sigset_t *oldset, struct pt_regs *regs, int in_syscall)
put_user(0xe0008200, &usp[3]);
put_user(0x34140000, &usp[4]);
- /* Stack is 64-byte aligned, and we only
- * need to flush 1 cache line */
- asm("fdc 0(%%sr3, %0)\n"
+ /* Stack is 64-byte aligned, and we only need
+ * to flush 1 cache line.
+ * Flushing one cacheline is cheap.
+ * "sync" on bigger (> 4 way) boxes is not.
+ */
+ asm("fdc %%r0(%%sr3, %0)\n"
"sync\n"
- "fic 0(%%sr3, %0)\n"
+ "fic %%r0(%%sr3, %0)\n"
"sync\n"
: : "r"(regs->gr[30]));