[PATCH] ppc32: Remove board support for ADIR

Support for the ADIR board is no longer maintained and thus being removed

Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

5 files changed, 0 insertions, 683 deletions

diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 5488a05..fcd03e5 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_CPU_FREQ_PMAC)	+= pmac_cpufreq.o
 endif
 obj-$(CONFIG_PMAC_BACKLIGHT)	+= pmac_backlight.o
 obj-$(CONFIG_PREP_RESIDUAL)	+= residual.o
-obj-$(CONFIG_ADIR)		+= adir_setup.o adir_pic.o adir_pci.o
 obj-$(CONFIG_PQ2ADS)		+= pq2ads.o
 obj-$(CONFIG_TQM8260)		+= tqm8260_setup.o
 obj-$(CONFIG_CPCI690)		+= cpci690.o
diff --git a/arch/ppc/platforms/adir.h b/arch/ppc/platforms/adir.h
deleted file mode 100644
index 13a748b..0000000
--- a/arch/ppc/platforms/adir.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * arch/ppc/platforms/adir.h
- *
- * Definitions for SBS Adirondack board support
- *
- * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
- */
-
-#ifndef __PPC_PLATFORMS_ADIR_H
-#define __PPC_PLATFORMS_ADIR_H
-
-/*
- * SBS Adirondack definitions
- */
-
-/* PPC physical address space layout. We use the one set up by the firmware. */
-#define	ADIR_PCI32_MEM_BASE	0x80000000
-#define	ADIR_PCI32_MEM_SIZE	0x20000000
-#define	ADIR_PCI64_MEM_BASE	0xA0000000
-#define	ADIR_PCI64_MEM_SIZE	0x20000000
-#define	ADIR_PCI32_IO_BASE	0xC0000000
-#define	ADIR_PCI32_IO_SIZE	0x10000000
-#define	ADIR_PCI64_IO_BASE	0xD0000000
-#define	ADIR_PCI64_IO_SIZE	0x10000000
-#define	ADIR_PCI64_PHB		0xFF400000
-#define	ADIR_PCI32_PHB		0xFF500000
-
-#define ADIR_PCI64_CONFIG_ADDR	(ADIR_PCI64_PHB + 0x000f8000)
-#define ADIR_PCI64_CONFIG_DATA	(ADIR_PCI64_PHB + 0x000f8010)
-
-#define ADIR_PCI32_CONFIG_ADDR	(ADIR_PCI32_PHB + 0x000f8000)
-#define ADIR_PCI32_CONFIG_DATA	(ADIR_PCI32_PHB + 0x000f8010)
-
-/* System memory as seen from PCI */
-#define ADIR_PCI_SYS_MEM_BASE	0x80000000
-
-/* Static virtual mapping of PCI I/O */
-#define	ADIR_PCI32_VIRT_IO_BASE	0xFE000000
-#define	ADIR_PCI32_VIRT_IO_SIZE	0x01000000
-#define	ADIR_PCI64_VIRT_IO_BASE	0xFF000000
-#define	ADIR_PCI64_VIRT_IO_SIZE	0x01000000
-
-/* Registers */
-#define	ADIR_NVRAM_RTC_ADDR	0x74
-#define	ADIR_NVRAM_RTC_DATA	0x75
-
-#define	ADIR_BOARD_ID_REG	(ADIR_PCI32_VIRT_IO_BASE + 0x08FFF0)
-#define	ADIR_CPLD1REV_REG	(ADIR_PCI32_VIRT_IO_BASE + 0x08FFF1)
-#define	ADIR_CPLD2REV_REG	(ADIR_PCI32_VIRT_IO_BASE + 0x08FFF2)
-#define	ADIR_FLASHCTL_REG	(ADIR_PCI32_VIRT_IO_BASE + 0x08FFF3)
-#define	ADIR_CPC710_STAT_REG	(ADIR_PCI32_VIRT_IO_BASE + 0x08FFF4)
-#define	ADIR_CLOCK_REG		(ADIR_PCI32_VIRT_IO_BASE + 0x08FFF5)
-#define	ADIR_GPIO_REG		(ADIR_PCI32_VIRT_IO_BASE + 0x08FFF8)
-#define	ADIR_MISC_REG		(ADIR_PCI32_VIRT_IO_BASE + 0x08FFF9)
-#define	ADIR_LED_REG		(ADIR_PCI32_VIRT_IO_BASE + 0x08FFFA)
-
-#define	ADIR_CLOCK_REG_PD	0x10
-#define	ADIR_CLOCK_REG_SPREAD	0x08
-#define	ADIR_CLOCK_REG_SEL133	0x04
-#define	ADIR_CLOCK_REG_SEL1	0x02
-#define	ADIR_CLOCK_REG_SEL0	0x01
-
-#define	ADIR_PROCA_INT_MASK	(ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF0)
-#define	ADIR_PROCB_INT_MASK	(ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF2)
-#define	ADIR_PROCA_INT_STAT	(ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF4)
-#define	ADIR_PROCB_INT_STAT	(ADIR_PCI32_VIRT_IO_BASE + 0x0EFFF6)
-
-/* Linux IRQ numbers */
-#define	ADIR_IRQ_NONE		-1
-#define	ADIR_IRQ_SERIAL2	3
-#define	ADIR_IRQ_SERIAL1	4
-#define	ADIR_IRQ_FDC		6
-#define	ADIR_IRQ_PARALLEL	7
-#define	ADIR_IRQ_VIA_AUDIO	10
-#define	ADIR_IRQ_VIA_USB	11
-#define	ADIR_IRQ_IDE0		14
-#define	ADIR_IRQ_IDE1		15
-#define	ADIR_IRQ_PCI0_INTA	16
-#define	ADIR_IRQ_PCI0_INTB	17
-#define	ADIR_IRQ_PCI0_INTC	18
-#define	ADIR_IRQ_PCI0_INTD	19
-#define	ADIR_IRQ_PCI1_INTA	20
-#define	ADIR_IRQ_PCI1_INTB	21
-#define	ADIR_IRQ_PCI1_INTC	22
-#define	ADIR_IRQ_PCI1_INTD	23
-#define	ADIR_IRQ_MBSCSI		24	/* motherboard SCSI */
-#define	ADIR_IRQ_MBETH1		25	/* motherboard Ethernet 1 */
-#define	ADIR_IRQ_MBETH0		26	/* motherboard Ethernet 0 */
-#define	ADIR_IRQ_CPC710_INT1	27
-#define	ADIR_IRQ_CPC710_INT2	28
-#define	ADIR_IRQ_VT82C686_NMI	29
-#define	ADIR_IRQ_VT82C686_INTR	30
-#define	ADIR_IRQ_INTERPROC	31
-
-#endif /* __PPC_PLATFORMS_ADIR_H */
diff --git a/arch/ppc/platforms/adir_pci.c b/arch/ppc/platforms/adir_pci.c
deleted file mode 100644
index f94ac53..0000000
--- a/arch/ppc/platforms/adir_pci.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * arch/ppc/platforms/adir_pci.c
- *
- * PCI support for SBS Adirondack
- *
- * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
- * based on the K2 version by Matt Porter <mporter@mvista.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-
-#include <syslib/cpc710.h>
-#include "adir.h"
-
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif /* DEBUG */
-
-static inline int __init
-adir_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-#define	PCIIRQ(a,b,c,d)	{ADIR_IRQ_##a,ADIR_IRQ_##b,ADIR_IRQ_##c,ADIR_IRQ_##d},
-	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
-	/*
-	 * The three PCI devices on the motherboard have dedicated lines to the
-	 * CPLD interrupt controller, bypassing the standard PCI INTA-D and the
-	 * PC interrupt controller. All other PCI devices (slots) have usual
-	 * staggered INTA-D lines, resulting in 8 lines total (PCI0 INTA-D and
-	 * PCI1 INTA-D). All 8 go to the CPLD interrupt controller. PCI0 INTA-D
-	 * also go to the south bridge, so we have the option of taking them
-	 * via the CPLD interrupt controller or via the south bridge 8259
-	 * 8258 thingy. PCI1 INTA-D can only be taken via the CPLD interrupt
-	 * controller. We take all PCI interrupts via the CPLD interrupt
-	 * controller as recommended by SBS.
-	 *
-	 * We also have some monkey business with the PCI devices within the
-	 * VT82C686B south bridge itself. This chip actually has 7 functions on
-	 * its IDSEL. Function 0 is the actual south bridge, function 1 is IDE,
-	 * and function 4 is some special stuff. The other 4 functions are just
-	 * regular PCI devices bundled in the chip. 2 and 3 are USB UHCIs and 5
-	 * and 6 are audio (not supported on the Adirondack).
-	 *
-	 * This is where the monkey business begins. PCI devices are supposed
-	 * to signal normal PCI interrupts. But the 4 functions in question are
-	 * located in the south bridge chip, which is designed with the
-	 * assumption that it will be fielding PCI INTA-D interrupts rather
-	 * than generating them. Here's what it does. Each of the functions in
-	 * question routes its interrupt to one of the IRQs on the 8259 thingy.
-	 * Which one? It looks at the Interrupt Line register in the PCI config
-	 * space, even though the PCI spec says it's for BIOS/OS interaction
-	 * only.
-	 *
-	 * How do we deal with this? We take these interrupts via 8259 IRQs as
-	 * we have to. We return the desired IRQ numbers from this routine when
-	 * called for the functions in question. The PCI scan code will then
-	 * stick our return value into the Interrupt Line register in the PCI
-	 * config space, and the interrupt will actually go there. We identify
-	 * these functions within the south bridge IDSEL by their interrupt pin
-	 * numbers, as the VT82C686B has 04 in the Interrupt Pin register for
-	 * USB and 03 for audio.
-	 */
-	if (!hose->index) {
-		static char pci_irq_table[][4] =
-		/*
-		 *             PCI IDSEL/INTPIN->INTLINE
-		 *             A          B          C          D
-		 */
-		{
-    /* south bridge */	PCIIRQ(IDE0,      NONE,      VIA_AUDIO, VIA_USB)
-    /* Ethernet 0 */	PCIIRQ(MBETH0,    MBETH0,    MBETH0,    MBETH0)
-    /* PCI0 slot 1 */	PCIIRQ(PCI0_INTB, PCI0_INTC, PCI0_INTD, PCI0_INTA)
-    /* PCI0 slot 2 */	PCIIRQ(PCI0_INTC, PCI0_INTD, PCI0_INTA, PCI0_INTB)
-    /* PCI0 slot 3 */	PCIIRQ(PCI0_INTD, PCI0_INTA, PCI0_INTB, PCI0_INTC)
-		};
-		const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	} else {
-		static char pci_irq_table[][4] =
-		/*
-		 *             PCI IDSEL/INTPIN->INTLINE
-		 *             A          B          C          D
-		 */
-		{
-    /* Ethernet 1 */	PCIIRQ(MBETH1,    MBETH1,    MBETH1,    MBETH1)
-    /* SCSI */		PCIIRQ(MBSCSI,    MBSCSI,    MBSCSI,    MBSCSI)
-    /* PCI1 slot 1 */	PCIIRQ(PCI1_INTB, PCI1_INTC, PCI1_INTD, PCI1_INTA)
-    /* PCI1 slot 2 */	PCIIRQ(PCI1_INTC, PCI1_INTD, PCI1_INTA, PCI1_INTB)
-    /* PCI1 slot 3 */	PCIIRQ(PCI1_INTD, PCI1_INTA, PCI1_INTB, PCI1_INTC)
-		};
-		const long min_idsel = 3, max_idsel = 7, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-#undef PCIIRQ
-}
-
-static void
-adir_pcibios_fixup_resources(struct pci_dev *dev)
-{
-	int i;
-
-	if ((dev->vendor == PCI_VENDOR_ID_IBM) &&
-			(dev->device == PCI_DEVICE_ID_IBM_CPC710_PCI64))
-	{
-		DBG("Fixup CPC710 resources\n");
-		for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
-		{
-			dev->resource[i].start = 0;
-			dev->resource[i].end = 0;
-		}
-	}
-}
-
-/*
- * CPC710 DD3 has an errata causing it to hang the system if a type 0 config
- * cycle is attempted on its PCI32 interface with a device number > 21.
- * CPC710's PCI bridges map device numbers 1 through 21 to AD11 through AD31.
- * Per the PCI spec it MUST accept all other device numbers and do nothing, and
- * software MUST scan all device numbers without assuming how IDSELs are
- * mapped. However, as the CPC710 DD3's errata causes such correct scanning
- * procedure to hang the system, we have no choice but to introduce this hack
- * of knowingly avoiding device numbers > 21 on PCI0,
- */
-static int
-adir_exclude_device(u_char bus, u_char devfn)
-{
-	if ((bus == 0) && (PCI_SLOT(devfn) > 21))
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	else
-		return PCIBIOS_SUCCESSFUL;
-}
-
-void adir_find_bridges(void)
-{
-	struct pci_controller *hose_a, *hose_b;
-
-	/* Setup PCI32 hose */
-	hose_a = pcibios_alloc_controller();
-	if (!hose_a)
-		return;
-
-	hose_a->first_busno = 0;
-	hose_a->last_busno = 0xff;
-	hose_a->pci_mem_offset = ADIR_PCI32_MEM_BASE;
-	hose_a->io_space.start = 0;
-	hose_a->io_space.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
-	hose_a->mem_space.start = 0;
-	hose_a->mem_space.end = ADIR_PCI32_MEM_SIZE - 1;
-	hose_a->io_resource.start = 0;
-	hose_a->io_resource.end = ADIR_PCI32_VIRT_IO_SIZE - 1;
-	hose_a->io_resource.flags = IORESOURCE_IO;
-	hose_a->mem_resources[0].start = ADIR_PCI32_MEM_BASE;
-	hose_a->mem_resources[0].end = ADIR_PCI32_MEM_BASE +
-					ADIR_PCI32_MEM_SIZE - 1;
-	hose_a->mem_resources[0].flags = IORESOURCE_MEM;
-	hose_a->io_base_phys = ADIR_PCI32_IO_BASE;
-	hose_a->io_base_virt = (void *) ADIR_PCI32_VIRT_IO_BASE;
-
-	ppc_md.pci_exclude_device = adir_exclude_device;
-	setup_indirect_pci(hose_a, ADIR_PCI32_CONFIG_ADDR,
-			   ADIR_PCI32_CONFIG_DATA);
-
-	/* Initialize PCI32 bus registers */
-	early_write_config_byte(hose_a,
-			hose_a->first_busno,
-			PCI_DEVFN(0, 0),
-			CPC710_BUS_NUMBER,
-			hose_a->first_busno);
-	early_write_config_byte(hose_a,
-			hose_a->first_busno,
-			PCI_DEVFN(0, 0),
-			CPC710_SUB_BUS_NUMBER,
-			hose_a->last_busno);
-
-	hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
-
-	/* Write out correct max subordinate bus number for hose A */
-	early_write_config_byte(hose_a,
-			hose_a->first_busno,
-			PCI_DEVFN(0, 0),
-			CPC710_SUB_BUS_NUMBER,
-			hose_a->last_busno);
-
-	/* Setup PCI64 hose */
-	hose_b = pcibios_alloc_controller();
-	if (!hose_b)
-		return;
-
-	hose_b->first_busno = hose_a->last_busno + 1;
-	hose_b->last_busno = 0xff;
-	hose_b->pci_mem_offset = ADIR_PCI64_MEM_BASE;
-	hose_b->io_space.start = 0;
-	hose_b->io_space.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
-	hose_b->mem_space.start = 0;
-	hose_b->mem_space.end = ADIR_PCI64_MEM_SIZE - 1;
-	hose_b->io_resource.start = 0;
-	hose_b->io_resource.end = ADIR_PCI64_VIRT_IO_SIZE - 1;
-	hose_b->io_resource.flags = IORESOURCE_IO;
-	hose_b->mem_resources[0].start = ADIR_PCI64_MEM_BASE;
-	hose_b->mem_resources[0].end = ADIR_PCI64_MEM_BASE +
-					ADIR_PCI64_MEM_SIZE - 1;
-	hose_b->mem_resources[0].flags = IORESOURCE_MEM;
-	hose_b->io_base_phys = ADIR_PCI64_IO_BASE;
-	hose_b->io_base_virt = (void *) ADIR_PCI64_VIRT_IO_BASE;
-
-	setup_indirect_pci(hose_b, ADIR_PCI64_CONFIG_ADDR,
-			   ADIR_PCI64_CONFIG_DATA);
-
-	/* Initialize PCI64 bus registers */
-	early_write_config_byte(hose_b,
-			0,
-			PCI_DEVFN(0, 0),
-			CPC710_SUB_BUS_NUMBER,
-			0xff);
-
-	early_write_config_byte(hose_b,
-			0,
-			PCI_DEVFN(0, 0),
-			CPC710_BUS_NUMBER,
-			hose_b->first_busno);
-
-	hose_b->last_busno = pciauto_bus_scan(hose_b,
-			hose_b->first_busno);
-
-	/* Write out correct max subordinate bus number for hose B */
-	early_write_config_byte(hose_b,
-			hose_b->first_busno,
-			PCI_DEVFN(0, 0),
-			CPC710_SUB_BUS_NUMBER,
-			hose_b->last_busno);
-
-	ppc_md.pcibios_fixup = NULL;
-	ppc_md.pcibios_fixup_resources = adir_pcibios_fixup_resources;
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = adir_map_irq;
-}
diff --git a/arch/ppc/platforms/adir_pic.c b/arch/ppc/platforms/adir_pic.c
deleted file mode 100644
index 9947cba..0000000
--- a/arch/ppc/platforms/adir_pic.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * arch/ppc/platforms/adir_pic.c
- *
- * Interrupt controller support for SBS Adirondack
- *
- * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
- * based on the K2 and SCM versions by Matt Porter <mporter@mvista.com>
- */
-
-#include <linux/stddef.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-
-#include <asm/io.h>
-#include <asm/i8259.h>
-#include "adir.h"
-
-static void adir_onboard_pic_enable(unsigned int irq);
-static void adir_onboard_pic_disable(unsigned int irq);
-
-__init static void
-adir_onboard_pic_init(void)
-{
-	volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
-
-	/* Disable all Adirondack onboard interrupts */
-	out_be16(maskreg, 0xFFFF);
-}
-
-static int
-adir_onboard_pic_get_irq(void)
-{
-	volatile u_short *statreg = (volatile u_short *) ADIR_PROCA_INT_STAT;
-	int irq;
-	u_short int_status, int_test;
-
-	int_status = in_be16(statreg);
-	for (irq = 0, int_test = 1; irq < 16; irq++, int_test <<= 1) {
-		if (int_status & int_test)
-			break;
-	}
-
-	if (irq == 16)
-		return -1;
-
-	return (irq+16);
-}
-
-static void
-adir_onboard_pic_enable(unsigned int irq)
-{
-	volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
-
-	/* Change irq to Adirondack onboard native value */
-	irq -= 16;
-
-	/* Enable requested irq number */
-	out_be16(maskreg, in_be16(maskreg) & ~(1 << irq));
-}
-
-static void
-adir_onboard_pic_disable(unsigned int irq)
-{
-	volatile u_short *maskreg = (volatile u_short *) ADIR_PROCA_INT_MASK;
-
-	/* Change irq to Adirondack onboard native value */
-	irq -= 16;
-
-	/* Disable requested irq number */
-	out_be16(maskreg, in_be16(maskreg) | (1 << irq));
-}
-
-static struct hw_interrupt_type adir_onboard_pic = {
-	" ADIR PIC ",
-	NULL,
-	NULL,
-	adir_onboard_pic_enable,		/* unmask */
-	adir_onboard_pic_disable,		/* mask */
-	adir_onboard_pic_disable,		/* mask and ack */
-	NULL,
-	NULL
-};
-
-static struct irqaction noop_action = {
-	.handler	= no_action,
-	.flags          = SA_INTERRUPT,
-	.mask           = CPU_MASK_NONE,
-	.name           = "82c59 primary cascade",
-};
-
-/*
- * Linux interrupt values are assigned as follows:
- *
- * 	0-15		VT82C686 8259 interrupts
- * 	16-31		Adirondack CPLD interrupts
- */
-__init void
-adir_init_IRQ(void)
-{
-	int	i;
-
-	/* Initialize the cascaded 8259's on the VT82C686 */
-	for (i=0; i<16; i++)
-		irq_desc[i].handler = &i8259_pic;
-	i8259_init(NULL);
-
-	/* Initialize Adirondack CPLD PIC and enable 8259 interrupt cascade */
-	for (i=16; i<32; i++)
-		irq_desc[i].handler = &adir_onboard_pic;
-	adir_onboard_pic_init();
-
-	/* Enable 8259 interrupt cascade */
-	setup_irq(ADIR_IRQ_VT82C686_INTR, &noop_action);
-}
-
-int
-adir_get_irq(struct pt_regs *regs)
-{
-	int	irq;
-
-	if ((irq = adir_onboard_pic_get_irq()) < 0)
-		return irq;
-
-	if (irq == ADIR_IRQ_VT82C686_INTR)
-		irq = i8259_irq(regs);
-
-	return irq;
-}
diff --git a/arch/ppc/platforms/adir_setup.c b/arch/ppc/platforms/adir_setup.c
deleted file mode 100644
index 6a6754e..0000000
--- a/arch/ppc/platforms/adir_setup.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * arch/ppc/platforms/adir_setup.c
- *
- * Board setup routines for SBS Adirondack
- *
- * By Michael Sokolov <msokolov@ivan.Harhan.ORG>
- * based on the K2 version by Matt Porter <mporter@mvista.com>
- */
-
-#include <linux/config.h>
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/ide.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-
-#include "adir.h"
-
-extern void adir_init_IRQ(void);
-extern int adir_get_irq(struct pt_regs *);
-extern void adir_find_bridges(void);
-extern unsigned long loops_per_jiffy;
-
-static unsigned int cpu_750cx[16] = {
-	5, 15, 14, 0, 4, 13, 0, 9, 6, 11, 8, 10, 16, 12, 7, 0
-};
-
-static int
-adir_get_bus_speed(void)
-{
-	if (!(*((u_char *) ADIR_CLOCK_REG) & ADIR_CLOCK_REG_SEL133))
-		return 100000000;
-	else
-		return 133333333;
-}
-
-static int
-adir_get_cpu_speed(void)
-{
-	unsigned long hid1;
-	int cpu_speed;
-
-	hid1 = mfspr(SPRN_HID1) >> 28;
-
-	hid1 = cpu_750cx[hid1];
-
-	cpu_speed = adir_get_bus_speed()*hid1/2;
-	return cpu_speed;
-}
-
-static void __init
-adir_calibrate_decr(void)
-{
-	int freq, divisor = 4;
-
-	/* determine processor bus speed */
-	freq = adir_get_bus_speed();
-	tb_ticks_per_jiffy = freq / HZ / divisor;
-	tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
-}
-
-static int
-adir_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: SBS\n");
-	seq_printf(m, "machine\t\t: Adirondack\n");
-	seq_printf(m, "cpu speed\t: %dMhz\n", adir_get_cpu_speed()/1000000);
-	seq_printf(m, "bus speed\t: %dMhz\n", adir_get_bus_speed()/1000000);
-	seq_printf(m, "memory type\t: SDRAM\n");
-
-	return 0;
-}
-
-extern char cmd_line[];
-
-TODC_ALLOC();
-
-static void __init
-adir_setup_arch(void)
-{
-	unsigned int cpu;
-
-	/* Setup TODC access */
-	TODC_INIT(TODC_TYPE_MC146818, ADIR_NVRAM_RTC_ADDR, 0,
-		  ADIR_NVRAM_RTC_DATA, 8);
-
-	/* init to some ~sane value until calibrate_delay() runs */
-        loops_per_jiffy = 50000000/HZ;
-
-       /* Setup PCI host bridges */
-        adir_find_bridges();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA1;
-#endif
-
-	/* Identify the system */
-	printk("System Identification: SBS Adirondack - PowerPC 750CXe @ %d Mhz\n", adir_get_cpu_speed()/1000000);
-	printk("SBS Adirondack port (C) 2001 SBS Technologies, Inc.\n");
-
-	/* Identify the CPU manufacturer */
-	cpu = mfspr(SPRN_PVR);
-	printk("CPU manufacturer: IBM [rev=%04x]\n", (cpu & 0xffff));
-}
-
-static void
-adir_restart(char *cmd)
-{
-	local_irq_disable();
-	/* SRR0 has system reset vector, SRR1 has default MSR value */
-	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
-	__asm__ __volatile__
-	("lis	3,0xfff0\n\t"
-	 "ori	3,3,0x0100\n\t"
-	 "mtspr	26,3\n\t"
-	 "li	3,0\n\t"
-	 "mtspr	27,3\n\t"
-	 "rfi\n\t");
-	for(;;);
-}
-
-static void
-adir_power_off(void)
-{
-	for(;;);
-}
-
-static void
-adir_halt(void)
-{
-	adir_restart(NULL);
-}
-
-static unsigned long __init
-adir_find_end_of_memory(void)
-{
-	return boot_mem_size;
-}
-
-static void __init
-adir_map_io(void)
-{
-	io_block_mapping(ADIR_PCI32_VIRT_IO_BASE, ADIR_PCI32_IO_BASE,
-				ADIR_PCI32_VIRT_IO_SIZE, _PAGE_IO);
-	io_block_mapping(ADIR_PCI64_VIRT_IO_BASE, ADIR_PCI64_IO_BASE,
-				ADIR_PCI64_VIRT_IO_SIZE, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	/*
-	 * On the Adirondack we use bi_recs and pass the pointer to them in R3.
-	 */
-	parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
-
-	/* Remember, isa_io_base is virtual but isa_mem_base is physical! */
-	isa_io_base = ADIR_PCI32_VIRT_IO_BASE;
-	isa_mem_base = ADIR_PCI32_MEM_BASE;
-	pci_dram_offset = ADIR_PCI_SYS_MEM_BASE;
-
-	ppc_md.setup_arch = adir_setup_arch;
-	ppc_md.show_cpuinfo = adir_show_cpuinfo;
-	ppc_md.irq_canonicalize = NULL;
-	ppc_md.init_IRQ = adir_init_IRQ;
-	ppc_md.get_irq = adir_get_irq;
-	ppc_md.init = NULL;
-
-	ppc_md.find_end_of_memory = adir_find_end_of_memory;
-	ppc_md.setup_io_mappings = adir_map_io;
-
-	ppc_md.restart = adir_restart;
-	ppc_md.power_off = adir_power_off;
-	ppc_md.halt = adir_halt;
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_mc146818_read_val;
-	ppc_md.nvram_write_val = todc_mc146818_write_val;
-	ppc_md.calibrate_decr = adir_calibrate_decr;
-}