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author | Paul Mundt <lethal@linux-sh.org> | 2009-08-15 10:48:13 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-15 10:48:13 +0900 |
commit | e82da214d2fe3dc2610df966100c4f36bc0fad91 (patch) | |
tree | 27904e62592da9c84499509cc85429644dcd0b93 /arch/sh/kernel/cpu | |
parent | aae4d1428c03b03f9fe6204a83e35822fe9cc591 (diff) | |
download | kernel_samsung_aries-e82da214d2fe3dc2610df966100c4f36bc0fad91.zip kernel_samsung_aries-e82da214d2fe3dc2610df966100c4f36bc0fad91.tar.gz kernel_samsung_aries-e82da214d2fe3dc2610df966100c4f36bc0fad91.tar.bz2 |
sh: Track the CPU family in sh_cpuinfo.
This adds a family member to struct sh_cpuinfo, which allows us to fall
back more on the probe routines to work out what sort of subtype we are
running on. This will be used by the CPU cache initialization code in
order to first do family-level initialization, followed by subtype-level
optimizations.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu')
-rw-r--r-- | arch/sh/kernel/cpu/sh2/probe.c | 1 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh2a/probe.c | 2 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh3/probe.c | 2 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4/probe.c | 9 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh5/probe.c | 2 |
5 files changed, 14 insertions, 2 deletions
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index 5916d90..1db6d88 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c @@ -29,6 +29,7 @@ int __init detect_cpu_and_cache_system(void) */ boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; boot_cpu_data.icache = boot_cpu_data.dcache; + boot_cpu_data.family = CPU_FAMILY_SH2; return 0; } diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index e098e2f..6825d65 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -15,6 +15,8 @@ int __init detect_cpu_and_cache_system(void) { + boot_cpu_data.family = CPU_FAMILY_SH2A; + /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ boot_cpu_data.flags |= CPU_HAS_OP32; diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c index 10f2a76..f9c7df6 100644 --- a/arch/sh/kernel/cpu/sh3/probe.c +++ b/arch/sh/kernel/cpu/sh3/probe.c @@ -107,5 +107,7 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void) boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; boot_cpu_data.icache = boot_cpu_data.dcache; + boot_cpu_data.family = CPU_FAMILY_SH3; + return 0; } diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index 6c78d0a..1148607 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -57,8 +57,12 @@ int __init detect_cpu_and_cache_system(void) * Setup some generic flags we can probe on SH-4A parts */ if (((pvr >> 16) & 0xff) == 0x10) { - if ((cvr & 0x10000000) == 0) + boot_cpu_data.family = CPU_FAMILY_SH4A; + + if ((cvr & 0x10000000) == 0) { boot_cpu_data.flags |= CPU_HAS_DSP; + boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP; + } boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER; boot_cpu_data.cut_major = pvr & 0x7f; @@ -68,6 +72,7 @@ int __init detect_cpu_and_cache_system(void) } else { /* And some SH-4 defaults.. */ boot_cpu_data.flags |= CPU_HAS_PTEA; + boot_cpu_data.family = CPU_FAMILY_SH4; } /* FPU detection works for everyone */ @@ -174,7 +179,7 @@ int __init detect_cpu_and_cache_system(void) break; default: - boot_cpu_data.type = CPU_SH_NONE; + boot_cpu_data.type = boot_cpu_data.family = CPU_SH_NONE; break; } diff --git a/arch/sh/kernel/cpu/sh5/probe.c b/arch/sh/kernel/cpu/sh5/probe.c index 92ad844..521d05b 100644 --- a/arch/sh/kernel/cpu/sh5/probe.c +++ b/arch/sh/kernel/cpu/sh5/probe.c @@ -34,6 +34,8 @@ int __init detect_cpu_and_cache_system(void) /* CPU.VCR aliased at CIR address on SH5-101 */ boot_cpu_data.type = CPU_SH5_101; + boot_cpu_data.family = CPU_FAMILY_SH5; + /* * First, setup some sane values for the I-cache. */ |