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| author | Jan Beulich <JBeulich@novell.com> | 2011-02-23 10:08:10 +0000 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-05-21 09:00:35 -0700 |
| commit | a3170c1f924ce2565c4e160b9b095e65c03b2dc6 (patch) | |
| tree | 70a3bd84066921f0c1c454f205f6031fa5f97a72 /arch/x86/pci | |
| parent | 51c2e0a7e5bc7ed1384cc68cfb95e702571500c9 (diff) | |
| download | kernel_samsung_aries-a3170c1f924ce2565c4e160b9b095e65c03b2dc6.zip kernel_samsung_aries-a3170c1f924ce2565c4e160b9b095e65c03b2dc6.tar.gz kernel_samsung_aries-a3170c1f924ce2565c4e160b9b095e65c03b2dc6.tar.bz2 | |
x86/PCI: derive pcibios_last_bus from ACPI MCFG
On various newer Intel systems the PCI bus(ses) the non-core devices
live on aren't getting announced by ACPI except through the bus range
covered by mmconfig. At least the i7core-edac driver depends on these
devices getting detected.
Mauro, could you check whether with this change the Xeon 55xx hack in
that driver can go away altogether, and with it the bogus exporting of
pcibios_scan_specific_bus()?
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Mauro Carvalho Chehab <mchehab@redhat.com>
Cc: Aristeu Sergio <arozansk@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch/x86/pci')
| -rw-r--r-- | arch/x86/pci/mmconfig-shared.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index e282886..750c346 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -606,6 +606,16 @@ static void __init __pci_mmcfg_init(int early) if (list_empty(&pci_mmcfg_list)) return; + if (pcibios_last_bus < 0) { + const struct pci_mmcfg_region *cfg; + + list_for_each_entry(cfg, &pci_mmcfg_list, list) { + if (cfg->segment) + break; + pcibios_last_bus = cfg->end_bus; + } + } + if (pci_mmcfg_arch_init()) pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; else { |