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| author | Jesse Barnes <jbarnes@hobbes.virtuousgeek.org> | 2008-02-07 17:33:28 -0800 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2008-02-20 09:42:12 +1000 |
| commit | c0c4261b6fd80f0fc5546ed67058592469a4f5b7 (patch) | |
| tree | 7edcdb723401994367ff595c5aa3ebfc1b74181e /drivers/char/drm | |
| parent | 0da3ea12fc2607beb67c2d54d0347807ea615573 (diff) | |
| download | kernel_samsung_aries-c0c4261b6fd80f0fc5546ed67058592469a4f5b7.zip kernel_samsung_aries-c0c4261b6fd80f0fc5546ed67058592469a4f5b7.tar.gz kernel_samsung_aries-c0c4261b6fd80f0fc5546ed67058592469a4f5b7.tar.bz2 | |
drm/i915: restore pipeconf regs unconditionally
On many chipsets, the checks for DPLL enable or VGA mode will prevent the pipeconf regs from being restored, which could result in a blank display or X failing to come back after resume. So restore them unconditionally along with actually restoring pipe B's palette correctly.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char/drm')
| -rw-r--r-- | drivers/char/drm/i915_drv.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c index 0f525ad..248e7b1 100644 --- a/drivers/char/drm/i915_drv.c +++ b/drivers/char/drm/i915_drv.c @@ -407,9 +407,7 @@ static int i915_resume(struct drm_device *dev) I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); } - if ((dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) && - (dev_priv->saveDPLL_A & DPLL_VGA_MODE_DIS)) - I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); + I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); i915_restore_palette(dev, PIPE_A); /* Enable the plane */ @@ -451,10 +449,9 @@ static int i915_resume(struct drm_device *dev) I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); } - if ((dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) && - (dev_priv->saveDPLL_B & DPLL_VGA_MODE_DIS)) - I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); - i915_restore_palette(dev, PIPE_A); + I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); + + i915_restore_palette(dev, PIPE_B); /* Enable the plane */ I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); I915_WRITE(DSPBBASE, I915_READ(DSPBBASE)); |