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| author | Bryan O'Donoghue <bryan.odonoghue@linux.intel.com> | 2012-04-18 17:37:39 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2012-05-07 08:56:32 -0700 |
| commit | 322fd620a858fab9c1ea85a7cfebe3fc041d7126 (patch) | |
| tree | fcb7cf40deb7342be11f5f7fdefec0f269632f75 /fs/autofs4 | |
| parent | 95cb2c603f27af05871e3e6718b6e1e1a6f59417 (diff) | |
| download | kernel_samsung_aries-322fd620a858fab9c1ea85a7cfebe3fc041d7126.zip kernel_samsung_aries-322fd620a858fab9c1ea85a7cfebe3fc041d7126.tar.gz kernel_samsung_aries-322fd620a858fab9c1ea85a7cfebe3fc041d7126.tar.bz2 | |
x86, apic: APIC code touches invalid MSR on P5 class machines
commit cbf2829b61c136edcba302a5e1b6b40e97d32c00 upstream.
Current APIC code assumes MSR_IA32_APICBASE is present for all systems.
Pentium Classic P5 and friends didn't have this MSR. MSR_IA32_APICBASE
was introduced as an architectural MSR by Intel @ P6.
Code paths that can touch this MSR invalidly are when vendor == Intel &&
cpu-family == 5 and APIC bit is set in CPUID - or when you simply pass
lapic on the kernel command line, on a P5.
The below patch stops Linux incorrectly interfering with the
MSR_IA32_APICBASE for P5 class machines. Other code paths exist that
touch the MSR - however those paths are not currently reachable for a
conformant P5.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linux.intel.com>
Link: http://lkml.kernel.org/r/4F8EEDD3.1080404@linux.intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'fs/autofs4')
0 files changed, 0 insertions, 0 deletions