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| author | Lin Ming <ming.m.lin@intel.com> | 2010-03-18 18:33:12 +0800 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-03-18 17:04:02 +0100 |
| commit | cb7d6b5053e86598735d9af19930f5929f007b7f (patch) | |
| tree | b707d913470443c05bd637d4b7fbab3926e0ba1c /fs/jbd2/Kconfig | |
| parent | f34edbc1cdb0f8f83d94e1d668dd6e41abf0defb (diff) | |
| download | kernel_samsung_aries-cb7d6b5053e86598735d9af19930f5929f007b7f.zip kernel_samsung_aries-cb7d6b5053e86598735d9af19930f5929f007b7f.tar.gz kernel_samsung_aries-cb7d6b5053e86598735d9af19930f5929f007b7f.tar.bz2 | |
perf, x86: Add cache events for the Pentium-4 PMU
Move the HT bit setting code from p4_pmu_event_map to
p4_hw_config. So the cache events can get HT bit set correctly.
Tested on my P4 desktop, below 6 cache events work:
L1-dcache-load-misses
LLC-load-misses
dTLB-load-misses
dTLB-store-misses
iTLB-loads
iTLB-load-misses
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Peter Zijlstra <peterz@infradead.org>
LKML-Reference: <1268908392.13901.128.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'fs/jbd2/Kconfig')
0 files changed, 0 insertions, 0 deletions