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| author | Michael S. Tsirkin <mst@redhat.com> | 2009-07-20 10:29:34 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-09-15 09:50:48 -0700 |
| commit | ccb86a6907c9ba7b5be5f521362fc308e80bed34 (patch) | |
| tree | e10f409f582a50243124d9b8bf38b2ec8be8d5ac /include/linux/pci_regs.h | |
| parent | a56af87648054089d89874b52e3fc23ed4f274ad (diff) | |
| download | kernel_samsung_aries-ccb86a6907c9ba7b5be5f521362fc308e80bed34.zip kernel_samsung_aries-ccb86a6907c9ba7b5be5f521362fc308e80bed34.tar.gz kernel_samsung_aries-ccb86a6907c9ba7b5be5f521362fc308e80bed34.tar.bz2 | |
uio: add generic driver for PCI 2.3 devices
This adds a generic uio driver that can bind to any PCI device. First
user will be virtualization where a qemu userspace process needs to give
guest OS access to the device.
Interrupts are handled using the Interrupt Disable bit in the PCI
command register and Interrupt Status bit in the PCI status register.
All devices compliant to PCI 2.3 (circa 2002) and all compliant PCI
Express devices should support these bits. Driver detects this support,
and won't bind to devices which do not support the Interrupt Disable Bit
in the command register.
It's expected that more features of interest to virtualization will be
added to this driver in the future. Possibilities are: mmap for device
resources, MSI/MSI-X, eventfd (to interface with kvm), iommu.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Chris Wright <chrisw@redhat.com>
Signed-off-by: Hans J. Koch <hjk@linutronix.de>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/pci_regs.h')
| -rw-r--r-- | include/linux/pci_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index fcaee42..dd0bed4 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -42,6 +42,7 @@ #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ #define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |