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| author | Vince Weaver <vince@deater.net> | 2009-07-08 17:46:14 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-07-10 10:28:26 +0200 |
| commit | 11d1578f9454159c43499d1d8fe8a7d728c176a3 (patch) | |
| tree | 2ad986dad1482083c1f61632f851883791d70aea /tools | |
| parent | 9590b7ba3fefdfe0c7741f5e2f61faf2ffcea19c (diff) | |
| download | kernel_samsung_aries-11d1578f9454159c43499d1d8fe8a7d728c176a3.zip kernel_samsung_aries-11d1578f9454159c43499d1d8fe8a7d728c176a3.tar.gz kernel_samsung_aries-11d1578f9454159c43499d1d8fe8a7d728c176a3.tar.bz2 | |
perf_counter: Add P6 PMU support
Add basic P6 PMU support. The P6 uses the EVNTSEL0 EN bit to
enable/disable both its counters. We use this for the
global enable/disable, and clear all config bits (except EN)
to disable individual counters.
Actual ia32 hardware doesn't support lfence, so use a locked
op without side-effect to implement a full barrier.
perf stat and perf record seem to function correctly.
[a.p.zijlstra@chello.nl: cleanups and complete the enable/disable code]
Signed-off-by: Vince Weaver <vince@deater.net>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <Pine.LNX.4.64.0907081718450.2715@pianoman.cluster.toy>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/perf/perf.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/tools/perf/perf.h b/tools/perf/perf.h index 27887c9..53bb955 100644 --- a/tools/perf/perf.h +++ b/tools/perf/perf.h @@ -1,7 +1,13 @@ #ifndef _PERF_PERF_H #define _PERF_PERF_H -#if defined(__x86_64__) || defined(__i386__) +#if defined(__i386__) +#include "../../arch/x86/include/asm/unistd.h" +#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") +#define cpu_relax() asm volatile("rep; nop" ::: "memory"); +#endif + +#if defined(__x86_64__) #include "../../arch/x86/include/asm/unistd.h" #define rmb() asm volatile("lfence" ::: "memory") #define cpu_relax() asm volatile("rep; nop" ::: "memory"); |