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* MIPS: Lantiq: Add PCI controller support.John Crispin2011-05-194-0/+432
| | | | | | | | | | | | | | | | The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds the driver that allows us to use the EBU as a PCI controller. In order for PCI to work the EBU is set to endianess swap all the data. In addition we need to make use of SWAP_IO_SPACE for device->host DMA to work. The clock of the PCI works in several modes (internal/external). If this is not configured correctly the SoC will hang. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2250/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: XLR, XLS: Add PCI support.Jayachandran C2011-05-192-0/+215
| | | | | | | | | | | | Adds pci/pci-xlr.c to support for XLR PCI/PCI-X interface and XLS PCIe interface. Update irq.c to ack PCI interrupts, use irq handler data to do the PCI/PCIe bus ack. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2337/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Fix common misspellingsLucas De Marchi2011-03-314-6/+6
| | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* MIPS: Convert the irq functions to the new namesThomas Gleixner2011-03-291-2/+2
| | | | | | Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* MIPS: Octeon: Rewrite interrupt handling code.David Daney2011-03-291-10/+10
| | | | | | | | | | | | | | | | | This includes conversion to new style irq_chip functions, and correctly enabling/disabling per-CPU interrupts. The hardware interrupt bit to irq number mapping is now done with a flexible map, instead of by bit twiddling the irq number. [ tglx: Adjusted to new irq_cpu_on/offline callbacks and __irq_set_affinity_lock ] Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org LKML-Reference: <1301081931-11240-5-git-send-email-ddaney@caviumnetworks.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* MIPS: MSP: Fix MSP71xx bpci interrupt handler return valueAnoop P A2011-03-141-2/+2
| | | | | | | | | Signed-off-by: Anoop P A <anoop.pa@gmail.com> To: Ben Hutchings <ben@decadent.org.uk> To: linux-mips@linux-mips.org To: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* tree-wide: fix comment/printk typosUwe Kleine-König2010-11-011-1/+1
| | | | | | | | | | "gadget", "through", "command", "maintain", "maintain", "controller", "address", "between", "initiali[zs]e", "instead", "function", "select", "already", "equal", "access", "management", "hierarchy", "registration", "interest", "relative", "memory", "offset", "already", Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* MIPS: Octeon: Rewrite DMA mapping functions.David Daney2010-10-292-6/+59
| | | | | | | | | | | | | All Octeon chips can support more than 4GB of RAM. Also due to how Octeon PCI is setup, even some configurations with less than 4GB of RAM will have portions that are not accessible from 32-bit devices. Enable the swiotlb code to handle the cases where a device cannot directly do DMA. This is a complete rewrite of the Octeon DMA mapping code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1639/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'for-next' of ↵Linus Torvalds2010-10-241-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (39 commits) Update broken web addresses in arch directory. Update broken web addresses in the kernel. Revert "drivers/usb: Remove unnecessary return's from void functions" for musb gadget Revert "Fix typo: configuation => configuration" partially ida: document IDA_BITMAP_LONGS calculation ext2: fix a typo on comment in ext2/inode.c drivers/scsi: Remove unnecessary casts of private_data drivers/s390: Remove unnecessary casts of private_data net/sunrpc/rpc_pipe.c: Remove unnecessary casts of private_data drivers/infiniband: Remove unnecessary casts of private_data drivers/gpu/drm: Remove unnecessary casts of private_data kernel/pm_qos_params.c: Remove unnecessary casts of private_data fs/ecryptfs: Remove unnecessary casts of private_data fs/seq_file.c: Remove unnecessary casts of private_data arm: uengine.c: remove C99 comments arm: scoop.c: remove C99 comments Fix typo configue => configure in comments Fix typo: configuation => configuration Fix typo interrest[ing|ed] => interest[ing|ed] Fix various typos of valid in comments ... Fix up trivial conflicts in: drivers/char/ipmi/ipmi_si_intf.c drivers/usb/gadget/rndis.c net/irda/irnet/irnet_ppp.c
| * Fix typo configue => configure in commentsThomas Weber2010-09-231-1/+1
| | | | | | | | | | | | Signed-off-by: Thomas Weber <weber@corscience.de> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | MIPS: Add missing #inclusions of <linux/irq.h>David Howells2010-10-072-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing #inclusions of <linux/irq.h> to a whole bunch of files that should really include it. Note that this can replace #inclusions of <asm/irq.h>. This is required for the patch to sort out irqflags handling function naming to compile on MIPS. The problem is that these files require access to things like setup_irq() - which isn't available by #including <linux/interrupt.h> Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Remove pr_<level> uses of KERN_<level>Joe Perches2010-10-041-1/+1
|/ | | | | | | | | | | These would result in KERN_<level> actually getting printed. Signed-off-by: Joe Perches <joe@perches.com> To: Jiri Kosina <trivial@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Allow more than 3.75GB of memory with PCIeDavid Daney2010-08-051-6/+31
| | | | | | | | | | | | | | | | | We reserve the 3.75GB - 4GB region of PCIe address space for device to device transfers, making the corresponding physical memory under direct mapping unavailable for DMA. To allow for PCIe DMA to all physical memory we map this chunk of physical memory with BAR1. Because of the resulting discontinuity in the mapping function, we remove a page of memory at each end of the range so multi-page DMA buffers can never be allocated that span the range. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1535/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Disallow MSI-X interrupt and fall back to MSI interrupts.Chandrakala Chavva2010-08-051-0/+28
| | | | | | | | | | | | | MSI-X interrupts are not supported yet for Octeon, return error if MSI-X interrupts are requested by driver so that the driver will fall back to use MSI interrupts. Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/1506/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: Octeon: Support 256 MSI on PCIeDavid Daney2010-08-051-117/+177
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Make MSI use handle_simple_irq().David Daney2010-08-051-46/+15
| | | | | | | | | | | | | | The use of handle_percpu_irq() is not really what we want for MSI, use handle_simple_irq() instead. This is probably the prototypical case for using handle_simple_irq(), because all the MSIs are dispatched from the root interrupt service routine. Also since the base IRQ is not shared, don't pass IRQF_SHARED. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1488/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Get rid of a bunch of MSI IRQ number definitions.David Daney2010-08-051-2/+2
| | | | | | | | | | MSI IRQ numbers are allocated dynamically, so there is no reason to have all these static definitions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Move MSI code out of octeon-irq.c.David Daney2010-08-051-2/+88
| | | | | | | | | | Put all the MSI code in one place (msi-octeon.c). This simplifies octeon-irq.c and gets rid of some ugly #ifdefs Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1484/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PCI: RM9000 checkpatch cleanupAndrea Gelmini2010-08-051-2/+2
| | | | | | | | | | | | arch/mips/pci/ops-titan-ht.c:36: ERROR: "foo * bar" should be "foo *bar" arch/mips/pci/ops-titan-ht.c:68: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: Tejun Heo <tj@kernel.org> Cc: Christoph Lameter <cl@linux-foundation.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1277/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Set io_map_base for several PCI bridges lacking itBen Hutchings2010-07-262-0/+2
| | | | | | | | | | | | | | | Several MIPS platforms don't set pci_controller::io_map_base for their PCI bridges. This results in a panic in pci_iomap(). (The panic is conditional on CONFIG_PCI_DOMAINS, but that is now enabled for all PCI MIPS systems.) Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: linux-mips@linux-mips.org Cc: Martin Michlmayr <tbm@cyrius.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: 584784@bugs.debian.org Patchwork: https://patchwork.linux-mips.org/patch/1377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SB1250: Include correct header and fix a warningSebastian Andrzej Siewior2010-04-301-1/+2
| | | | | | | | | | | | | | arch/mips/pci/pci-sb1250.c: In function sb1250_pcibios_init: | arch/mips/pci/pci-sb1250.c:257: warning: assignment makes integer from pointer without a cast | arch/mips/pci/pci-sb1250.c:285: error: MAX_NR_CONSOLES undeclared (first use in this function) | arch/mips/pci/pci-sb1250.c:285: error: (Each undeclared identifier is reported only once | arch/mips/pci/pci-sb1250.c:285: error: for each function it appears in.) Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lemote 2F: Ensure atomic execution of _rdmsr and _wrmsrWu Zhangjin2010-04-121-0/+10
| | | | | | | | | | | | | On Lemote 2F CS5536 MSRs are accessed through a index / data register pair. The access sequence must be protected by a spinlock to be atomic. Without this rebooting in fs2f_reboot() may fail. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1058/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* include cleanup: Update gfp.h and slab.h includes to prepare for breaking ↵Tejun Heo2010-03-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
* MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addressesBjorn Helgaas2010-02-272-2/+61
| | | | | | | | | | | | | | | | | | | | | | | | The GT-64111 PCI host bridge has no address translation mechanism, so it can't generate legacy port accesses. This quirk fixes legacy device port resources to contain the bus addresses actually generated by the GT-64111. I think this is the approach Ben Herrenschmidt suggested long ago: http://marc.info/?l=linux-kernel&m=119733290624544&w=2 This allows us to remove the IORESOURCE_PCI_FIXED hack from pcibios_fixup_device_resources(), which converts bus addresses to CPU addresses. IORESOURCE_PCI_FIXED denotes resources that can't be moved; it has nothing to do with converting bus to CPU addresses. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yoichi Yuasa <yuasa@linux-mips.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linux-mips@linux-mips.org Tested-by: Yoichi Yuasa <yuasa@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/998/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make various locks static.Ralf Baechle2010-02-271-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Nuke trailing blank linesRalf Baechle2010-02-271-1/+0
| | | | | | | Recent git versions now warn about those and they've always been a bit of an annoyance. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cleanup switches with cases that can be mergedRoel Kluin2010-02-271-4/+2
| | | | | | | | | Signed-off-by: Roel Kluin <roel.kluin@gmail.com> To: linux-mips@linux-mips.org To: Andrew Morton <akpm@linux-foundation.org> To: LKML <linux-kernel@vger.kernel.org> Patchwork: http://patchwork.linux-mips.org/patch/860/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Change the Email address of Wu ZhangjinWu Zhangjin2010-02-271-3/+1
| | | | | | | | | | | | Currently wuzj@lemote.com is not usable; change it to wuzhangjin@gmail.com. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: zhangfx@lemote.com Patchwork: http://patchwork.linux-mips.org/patch/829/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Lemote-2F: USB: Not Emulate Non-Posted WritesWu Zhangjin2010-02-271-1/+1
| | | | | | | | | | | | | | | Without this patch, when copying large amounts of data between the USB storage devices and the hard disk, the USB device will disconnect regularly. Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: zhangfx@lemote.com Patchwork: http://patchwork.linux-mips.org/patch/822/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* resource/PCI: mark struct resource as constDominik Brodowski2010-02-221-1/+1
| | | | | | | | | | | Now that we return the new resource start position, there is no need to update "struct resource" inside the align function. Therefore, mark the struct resource as const. Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* resource/PCI: align functions now return start of resourceDominik Brodowski2010-02-221-2/+2
| | | | | | | | | | | As suggested by Linus, align functions should return the start of a resource, not void. An update of "res->start" is no longer necessary. Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* MIPS: eXcite: Remove platform.Ralf Baechle2009-12-173-186/+0
| | | | | | | | | | | | | The platform has never been fully merged Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Koeller <thomas.koeller@baslerweb.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-kernel@vger.kernel.org Cc: linux-mtd@lists.infradead.org Acked-by: David Woodhouse <David.Woodhouse@intel.com> Acked-by: Wim Van Sebroeck <wim@iguana.be>
* MIPS: Lemote 2F: Add PCI supportWu Zhangjin2009-12-173-1/+216
| | | | | | | | | | | | | | | | | | PCI support for the Fuloong 2E and Lemote Loongson 2F family machines is mostly identical with the exception of CS5536 support. Rename ops-fuloong2e.c to ops-loongson2.c then add the CS5536 support to share most of the source code among Loongson machines. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: zhangfx@lemote.com Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: Nicholas Mc Guire <hofrat@hofr.at> Cc: Arnaud Patard <apatard@mandriva.com> Cc: loongson-dev@googlegroups.com Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Bonito64: Make Loongson independent from Bonito64 code.Wu Zhangjin2009-12-174-10/+158
| | | | | | | | | | | | | | | | | | The built-in Loongson 2E/2F northbridge in is bonito64-compatible but not identical with it. To avoid influencing the original bonito64 support and make the loongson support more maintainable, it's better to separate the Bonito64 code from the Loongson code. This also prepares the kernel for the coming Loongson 2f machines family support. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: Zhang Le <r0bertz@gentoo.org> Cc: zhangfx@lemote.com, Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MSP71xx: request_irq() failure ignored in msp_pcibios_config_access()Roel Kluin2009-09-301-1/+4
| | | | | | | | | Produce an error if request_irq() fails. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Cc: "Ithamar R. Adema" <ithamar.adema@team-embedded.nl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs.Maxime Bizon2009-09-175-0/+741
| | | | | | Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove useless zero initializations.Ralf Baechle2009-09-174-5/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Change naming methodsWu Zhangjin2009-09-173-3/+3
| | | | | | | | | | | | To make source code of loongson sharable to the machines(such as gdium) made by the other companies, we rename arch/mips/lemote to arch/mips/loongson, asm/mach-lemote to asm/mach-loongson, and rename lm2e to the name of the machine: fuloong-2e. accordingly, FULONG are renamed to FULOONG2E to make it distinguishable to the future FULOONG2F. and also, some other relative tuning is needed. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: clean up the coding styleWu Zhangjin2009-09-171-18/+0
| | | | | | | | | | | | | | | | | | With the help of script/checkpatch.pl, i have cleaned up the coding style. 1. remove un-needed header files and tune some comments. 2. remove some un-needed { } add a new header file loongson.h: 3. move some common header files to loongson.h 4. move some common extern declartions to loongson.h and this new header file is needed for future loongson2f support. Signed-off-by: Wu Zhangjin <wuzj@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon PCIe: Make hardware and software bus numbers match.David Daney2009-08-031-14/+17
| | | | | | | | Some SiliconImage PCIe SATA controlers are not detected when the bus numbers differ. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Eleminate filenames from commentsRalf Baechle2009-08-037-17/+0
| | | | | | | | | | They tend to get not updated when files are moved around or copied and lack any obvious use. While at it zap some only too obvious comments and as per Shinya's suggestion, add a copyright header to extable.c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Acked-by: Thadeu Lima de Souza Cascardo <cascardo@holoscopio.com>
* MIPS: Reorganize Cavium OCTEON PCI support.David Daney2009-07-034-0/+2337
| | | | | | | | | Move the cavium PCI files to the arch/mips/pci directory. Also cleanup comment formatting and code layout. Code from pci-common.c, was moved into other files. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Update Yoichi Yuasa's e-mail addressYoichi Yuasa2009-07-038-13/+13
| | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle2009-06-241-0/+1
| | | | | | | | | Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: RC32434: Define io_map_base for PCI controllerPhil Sutter2009-01-301-0/+11
| | | | | | | | | | | The code is rather based on trial-and-error than knowledge. Verified Via Rhine functionality in PIO as well as MMIO mode. [Looks sane -- Ralf] Signed-off-by: Phil Sutter <n0-1@freewrt.org> Tested-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* PCI: mips: use generic INTx swizzle from PCI coreBjorn Helgaas2009-01-071-16/+1
| | | | | | | | | | | Use the generic pci_common_swizzle() instead of arch-specific code. Note that pci_common_swizzle() loops based on dev->bus->self, not dev->bus->parent as the mips common_swizzle() did. I think they are equivalent for this purpose. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: mips: use generic pci_swizzle_interrupt_pin()Bjorn Helgaas2009-01-072-14/+1
| | | | | | | | Use the generic pci_swizzle_interrupt_pin() instead of arch-specific code. Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* MIPS: Better than nothing implementation of PCI mmap to fix X.Ralf Baechle2008-12-091-0/+24
| | | | | | | | | | | | Certain X11 servers such as the SIS server will only work if PCI mmap is implemented. This patch implements PCI mmap but to be on the same side so close to a release it only supports uncached mappings so performance will not be optimal for some uses such as framebuffers. Thanks to Zhang Le <r0bertz@gentoo.org> for the original report and testing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: EMMA: Move <asm/emma2rh> to <asm/emma> dirShinya Kuribayashi2008-10-273-3/+3
| | | | | | | We'll put all EMMA related headers there in the future. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: EMMA: Kconfig reorganizationShinya Kuribayashi2008-10-271-1/+1
| | | | | | | | | - Move EMMA related stuff into arch/mips/emma/Kconfig - Create CONFIG_SOC_EMMA* to handle more EMMA SoCs effectively - Rename CONFIG_MARKEINS into CONFIG_NEC_MARKEINS Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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